Specifications

Bit Field Description Effect on
Software
Available
15 Reserved
16 Reserved
17 Reserved
18 Reserved
19
TLB_RE
Recoverable (1 bit) ECC error in TLB RAM (hardware read of
TLB)
None MMU
present
20
TLB_UE
Unrecoverable (2 bit) ECC error in TLB RAM (hardware read of
TLB)
Possibly fatal MMU
present
21
TLB_SW
Software-triggered (1, 2, or 3 bit) ECC error in software read of
TLB
Possibly fatal MMU
present
22 Reserved
23 Reserved
24 Reserved
25 Reserved
26 Reserved
27 Reserved
28 Reserved
29 Reserved
JTAG Debug Module
The Nios II/f core supports the JTAG debug module to provide a JTAG interface to software debugging
tools. The Nios II/f core supports an optional enhanced interface that allows real-time trace data to be
routed out of the processor and stored in an external debug probe.
Note:
The Nios II MMU does not support the JTAG debug module trace.
Nios II/s Core
The Nios II/s standard core is designed for small core size. On-chip logic and memory resources are
conserved at the expense of execution performance. The Nios II/s core uses approximately 20% less logic
than the Nios II/f core, but execution performance also drops by roughly 40%. Altera designed the
Nios II/s core with the following design goals in mind:
• Do not cripple performance for the sake of size.
• Remove hardware features that have the highest ratio of resource usage to performance impact.
The resulting core is optimal for cost-sensitive, medium-performance applications. This includes applica‐
tions with large amounts of code and/or data, such as systems running an operating system in which
performance is not the highest priority.
NII51015
2015.04.02
JTAG Debug Module
5-15
Nios II Core Implementation Details
Altera Corporation
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