Specifications

• Instruction cache
• ECC errors (1, 2, or 3 bits) that occur in the instruction cache are recoverable; the Nios II processor
flushes the cache line and reads from external memory instead of correcting the ECC error.
• Register file
• 1 bit ECC errors are recoverable
• 2 bit ECC errors are not recoverable and generate ECC exceptions
• MMU TLB
• 1 bit ECC errors triggered by hardware reads are recoverable
• 2 bit ECC errors triggered by hardware reads are not recoverable and generate ECC exception.
• 1 or 2 bit ECC errors triggered by software reads to the TLBMISC register do not trigger an
exception, instead, TLBMISC.EE is set to 1. Software must read this field and invalidate/overwrite
the TLB entry.
The ECC interface is an Avalon-ST source with the output signal ecc_event_bus. This interface allows
external logic to monitor ECC errors in the Nios II processor.
The ecc_event_bus contains the ECC error signals that are driven to 1 even if ECC checking is disabled
in the Nios II processor (when CONFIG.ECCEN or CONFIG.ECCEXC is 0). The following table describes the
ECC error signals.
Table 5-11: ECC Error Signals
Bit
Field Description Effect on
Software
Available
0
EEH
ECC error exception while in exception handler mode (i.e.,
STATUS.EH = 1).
Likely fatal Always
1
RF_RE
Recoverable (1 bit) ECC error in register file RAM None Always
2
RF_UE
Unrecoverable (2 bit) ECC error in register file RAM Likely fatal Always
3
ICTAG_RE
Recoverable (1, 2, or 3 bit) ECC error in instruction cache tag
RAM
None Instruction
cache
present
4
ICDAT_RE
Recoverable (1, 2, or 3 bit) ECC error in instruction cache data
RAM.
None Instruction
cache
present
5 Reserved
6 Reserved
7 Reserved
8 Reserved
9 Reserved
10 Reserved
11 Reserved
12 Reserved
13 Reserved
14 Reserved
5-14
ECC
NII51015
2015.04.02
Altera Corporation
Nios II Core Implementation Details
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