Specifications

Instruction Cycles Penalties
store (without Avalon-MM transfer) 1
store (with Avalon-MM transfer) > 1
flushd, flushda (without Avalon-MM transfer) 2
flushd, flushda (with Avalon-MM transfer) > 2
initd, initda 2
flushi, initi 4
Multiply Late result
Divide Late result
Shift/rotate (with hardware multiply using embedded multipliers) 1 Late result
Shift/rotate (with hardware multiply using LE-based multipliers) 2 Late result
Shift/rotate (without hardware multiply present) 1 to 32 Late result
All other instructions 1
For Multiply and Divide, the number of cycles depends on the hardware multiply or divide option. Refer
to "Arithmetic Logic Unit" and "Instruction and Data Caches" s for details.
In the default Nios II/f configuration, instructions trap, break, eret, bret, flushp, wrctl, wrprs
require four clock cycles. If any of the following options are present, they require five clock cycles:
• MMU
• MPU
• Division exception
• Misaligned load/store address exception
• Extra exception information
• EIC port
• Shadow register sets
Related Information
• Data Cache on page 5-8
• Instruction and Data Caches on page 5-6
• Arithmetic Logic Unit on page 5-4
Exception Handling
The Nios II/f core supports the following exception types:
• Hardware interrupts
• Software trap
• Illegal instruction
• Unimplemented instruction
• Supervisor-only instruction (MMU or MPU only)
• Supervisor-only instruction address (MMU or MPU only)
• Supervisor-only data address (MMU or MPU only)
• Misaligned data address
• Misaligned destination address
5-12
Exception Handling
NII51015
2015.04.02
Altera Corporation
Nios II Core Implementation Details
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