Specifications

The A-stage stall occurs if any of the following conditions occurs:
• An A-stage memory instruction is waiting for Avalon-MM data master requests to complete. Typically
this happens when a load or store misses in the data cache, or a flushd instruction needs to write back
a dirty line.
• An A-stage shift/rotate instruction is still performing its operation. This only occurs with the
multicycle shift circuitry (i.e., when the hardware multiplier is not available).
• An A-stage divide instruction is still performing its operation. This only occurs when the optional
divide circuitry is available.
• An A-stage multicycle custom instruction is asserting its stall signal. This only occurs if the design
includes multicycle custom instructions.
The D-stage stall occurs if an instruction is trying to use the result of a late result instruction too early and
no M-stage pipeline flush is active. The late result instructions are loads, shifts, rotates, rdctl, multiplies
(if hardware multiply is supported), divides (if hardware divide is supported), and multicycle custom
instructions (if present).
Branch Prediction
The Nios II/f core performs dynamic branch prediction to minimize the cycle penalty associated with
taken branches.
Instruction Performance
All instructions take one or more cycles to execute. Some instructions have other penalties associated with
their execution. Late result instructions have two cycles placed between them and an instruction that uses
their result. Instructions that flush the pipeline cause up to three instructions after them to be cancelled.
This creates a three-cycle penalty and an execution time of four cycles. Instructions that require Avalon-
MM transfers are stalled until any required Avalon-MM transfers (up to one write and one read) are
completed.
Table 5-9: Instruction Execution Performance for Nios II/f Core 4byte/line data cache
Instruction Cycles Penalties
Normal ALU instructions (e.g., add, cmplt) 1
Combinatorial custom instructions 1
Multicycle custom instructions > 1 Late result
Branch (correctly predicted, taken) 2
Branch (correctly predicted, not taken) 1
Branch (mispredicted) 4 Pipeline flush
trap, break, eret, bret, flushp, wrctl, wrprs; illegal and unimple‐
mented instructions
4 or 5 Pipeline flush
call, jmpi, rdprs 2
jmp, ret, callr 3
rdctl 1 Late result
load (without Avalon-MM transfer) 1 Late result
load (with Avalon-MM transfer) > 1 Late result
NII51015
2015.04.02
Branch Prediction
5-11
Nios II Core Implementation Details
Altera Corporation
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