Specifications
The μTLBs are not visible to software. They act as an inclusive cache of the main TLB. The processor firsts
look for a hit in the μTLB. If it misses, it then looks for a hit in the main TLB. If the main TLB misses, the
processor takes an exception. If the main TLB hits, the TLB entry is copied into the μTLB for future
accesses.
The hardware automatically flushes the μTLB on each TLB write operation and on a wrctl to the tlbmisc
register in case the process identifier (PID) has changed.
Memory Protection Unit
The Nios II/f core provides options to improve the performance of the Nios II MPU.
For information about the MPU architecture, refer to the Programming Model chapter of the Nios II
Processor Reference Handbook.
Related Information
• Programming Model on page 3-1
• Programming Model
Execution Pipeline
This section provides an overview of the pipeline behavior for the benefit of performance-critical
applications. Designers can use this information to minimize unnecessary processor stalling. Most
application programmers never need to analyze the performance of individual instructions.
The Nios II/f core employs a 6-stage pipeline.
Table 5-8: Implementation Pipeline Stages for Nios II/f Core
Stage Letter Stage Name
F Fetch
D Decode
E Execute
M Memory
A Align
W Writeback
Up to one instruction is dispatched and/or retired per cycle. Instructions are dispatched and retired in
order. Dynamic branch prediction is implemented using a 2-bit branch history table. The pipeline stalls
for the following conditions:
• Multicycle instructions
• Avalon-MM instruction master port read accesses
• Avalon-MM data master port read/write accesses
• Data dependencies on long latency instructions (e.g., load, multiply, shift).
Pipeline Stalls
The pipeline is set up so that if a stage stalls, no new values enter that stage or any earlier stages. No
“catching up” of pipeline stages is allowed, even if a pipeline stage is empty.
Only the A-stage and D-stage are allowed to create stalls.
5-10
Memory Protection Unit
NII51015
2015.04.02
Altera Corporation
Nios II Core Implementation Details
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