Specifications

Related Information
• Instruction Set Reference on page 8-1
• Instruction Set Reference
• Processor Architecture on page 2-1
• Processor Architecture
Bursting
When the data cache is enabled, you can enable bursting on the data master port. Consult the
documentation for memory devices connected to the data master port to determine whether bursting can
improve performance.
Tightly-Coupled Memory
The Nios II/f core provides optional tightly-coupled memory interfaces for both instructions and data. A
Nios II/f core can use up to four each of instruction and data tightly-coupled memories. When a tightly-
coupled memory interface is enabled, the Nios II core includes an additional memory interface master
port. Each tightly-coupled memory interface must connect directly to exactly one memory slave port.
When tightly-coupled memory is present, the Nios II core decodes addresses internally to determine if
requested instructions or data reside in tightly-coupled memory. If the address resides in tightly-coupled
memory, the Nios II core fetches the instruction or data through the tightly-coupled memory interface.
Software accesses tightly-coupled memory with the usual load and store instructions, such as ldw or
ldwio.
Accessing tightly-coupled memory bypasses cache memory. The processor core functions as if cache were
not present for the address span of the tightly-coupled memory. Instructions for managing cache, such as
initd and flushd, do not affect the tightly-coupled memory, even if the instruction specifies an address
in tightly-coupled memory.
When the MMU is present, tightly-coupled memories are always mapped into the kernel partition and
can only be accessed in supervisor mode.
Memory Management Unit
The Nios II/f core provides options to improve the performance of the Nios II MMU.
For information about the MMU architecture, refer to the Programming Model chapter of the Nios II
Processor Reference Handbook.
Related Information
• Programming Model on page 3-1
• Programming Model
Micro Translation Lookaside Buffers
The translation lookaside buffer (TLB) consists of one main TLB stored in on-chip RAM and two separate
micro TLBs (μTLB) for instructions μITLB) and data (μDTLB) stored in LE-based registers.
The TLBs have a configurable number of entries and are fully associative. The default configuration has 6
μDTLB entries and 4 μITLB entries. The hardware chooses the least-recently used μTLB entry when
loading a new entry.
NII51015
2015.04.02
Bursting
5-9
Nios II Core Implementation Details
Altera Corporation
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