Specifications

Data Cache
The data cache memory has the following characteristics:
• Direct-mapped cache implementation
• Configurable line size of 4, 16, or 32 bytes
• The data master port reads an entire cache line at a time from memory, and issues one read per clock
cycle.
• Write-back
• Write-allocate (i.e., on a store instruction, a cache miss allocates the line for that address)
• Virtually-indexed, physically-tagged, when MMU present
The size of the tag field depends on the size of the cache memory and the physical address size. The size of
the line field depends only on the size of the cache memory. The size of the offset field depends on the line
size. Line sizes of 4, 16, and 32 bytes have offset widths of 2, 4, and 5 bits respectively. The maximum data
byte address size is 31 bits in systems without an MMU present. In systems with an MMU, the maximum
data byte address size is 32 bits and the tag field always includes all the bits of the PFN.
The data cache is optional. If the data cache is excluded from the core, the data master port can also be
excluded.
The Nios II instruction set provides several different instructions to clear the data cache. There are two
important questions to answer when determining the instruction to use. Do you need to consider the tag
field when looking for a cache match? Do you need to write dirty cache lines back to memory before
clearing? Below the table lists the most appropriate instruction to use for each case.
Table 5-7: Data Cache Clearing Instructions
Instruction Ignore Tag Field Consider Tag Field
Write Dirty Lines flushd flushda
Do Not Write Dirty Lines initd initda
Note: The 4-byte line data cache implementation substitutes the flushd instruction for the flushda
instruction and triggers an unimplemented instruction exception for the initda instruction. The
16-byte and 32-byte line data cache implementations fully support the flushda and initda
instructions.
For more information regarding the Nios II instruction set, refer to the Instruction Set Reference chapter
of the Nios II Processor Reference Handbook.
The Nios II/f core implements all the data cache bypass methods.
For information regarding the data cache bypass methods, refer to the Processor Architecture chapter of
the Nios II Processor Reference Handbook
Mixing cached and uncached accesses to the same cache line can result in invalid data reads. For example,
the following sequence of events causes cache incoherency.
1. The Nios II core writes data to cache, creating a dirty data cache line.
2. The Nios II core reads data from the same address, but bypasses the cache.
Note:
Avoid mixing cached and uncached accesses to the same cache line, regardless whether you are
reading from or writing to the cache line. If it is necessary to mix cached and uncached data
accesses, flush the corresponding line of the data cache after completing the cached accesses and
before performing the uncached accesses.
5-8
Data Cache
NII51015
2015.04.02
Altera Corporation
Nios II Core Implementation Details
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