Specifications

Bit Fields
line offset
Table 5-5: Cache Virtual Byte Address Fields
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
line
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
line offset
Table 5-6: Cache Physical Byte Address Fields
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
tag
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
offset
Instruction Cache
The instruction cache memory has the following characteristics:
• Direct-mapped cache implementation.
• 32 bytes (8 words) per cache line.
• The instruction master port reads an entire cache line at a time from memory, and issues one read per
clock cycle.
• Critical word first.
• Virtually-indexed, physically-tagged, when MMU present.
The size of the tag field depends on the size of the cache memory and the physical address size. The size of
the line field depends only on the size of the cache memory. The offset field is always five bits (i.e., a 32-
byte line). The maximum instruction byte address size is 31 bits in systems without an MMU present. In
systems with an MMU, the maximum instruction byte address size is 32 bits and the tag field always
includes all the bits of the physical frame number (PFN).
The instruction cache is optional. However, excluding instruction cache from the Nios II/f core requires
that the core include at least one tightly-coupled instruction memory.
NII51015
2015.04.02
Instruction Cache
5-7
Nios II Core Implementation Details
Altera Corporation
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