Specifications

Shift and Rotate Performance
The performance of shift operations depends on the hardware multiply option. When a hardware
multiplier is present, the ALU achieves shift and rotate operations in three or four clock cycles. Otherwise,
the ALU includes dedicated shift circuitry that achieves one-bit-per-cycle shift and rotate performance.
Refer to the "Instruction Execution Performance for Nios II/f Core" table in the "Instruction Performance"
section for details.
Related Information
Instruction Performance on page 5-11
Memory Access
The Nios II/f core provides optional instruction and data caches. The cache size for each is user-definable,
between 512 bytes and 64 KB.
The memory address width in the Nios II/f core depends on whether the optional MMU is present.
Without an MMU, the Nios II/f core supports the bit-31 cache bypass method for accessing I/O on the
data master port. Therefore addresses are 31 bits wide, reserving bit 31 for the cache bypass function.
With an MMU, cache bypass is a function of the memory partition and the contents of the translation
lookaside buffer (TLB). Therefore bit-31 cache bypass is disabled, and 32 address bits are available to
address memory.
Instruction and Data Master Ports
The instruction master port is a pipelined Avalon
®
Memory-Mapped (Avalon-MM) master port. If the
core includes data cache with a line size greater than four bytes, then the data master port is a pipelined
Avalon-MM master port. Otherwise, the data master port is not pipelined.
The instruction and data master ports on the Nios II/f core are optional. A master port can be excluded, as
long as the core includes at least one tightly-coupled memory to take the place of the missing master port.
Note:
Although the Nios II processor can operate entirely out of tightly-coupled memory without the
need for Avalon-MM instruction or data masters, software debug is not possible when either the
Avalon-MM instruction or data master is omitted.
Support for pipelined Avalon-MM transfers minimizes the impact of synchronous memory with pipeline
latency. The pipelined instruction and data master ports can issue successive read requests before prior
requests complete.
Instruction and Data Caches
This section first describes the similar characteristics of the instruction and data cache memories, and
then describes the differences.
Both the instruction and data cache addresses are divided into fields based on whether or not an MMU is
present in your system.
Table 5-4: Cache Byte Address Fields
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
tag line
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
5-6
Shift and Rotate Performance
NII51015
2015.04.02
Altera Corporation
Nios II Core Implementation Details
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