Specifications

The Nios II/f fast core is designed for high execution performance. Performance is gained at the expense
of core size. The base Nios II/f core, without the memory management unit (MMU) or memory
protection unit (MPU), is approximately 25% larger than the Nios II/s core. Altera designed the Nios II/f
core with the following design goals in mind:
• Maximize the instructions-per-cycle execution efficiency
• Optimize interrupt latency
• Maximize f
MAX
performance of the processor core
The resulting core is optimal for performance-critical applications, as well as for applications with large
amounts of code and/or data, such as systems running a full-featured operating system.
Overview
The Nios II/f core:
• Has separate optional instruction and data caches
• Provides optional MMU to support operating systems that require an MMU
• Provides optional MPU to support operating systems and runtime environments that desire memory
protection but do not need virtual memory management
• Can access up to 2 GB of external address space when no MMU is present and 4 GB when the MMU is
present
• Supports optional external interrupt controller (EIC) interface to provide customizable interrupt
prioritization
• Supports optional shadow register sets to improve interrupt latency
• Supports optional tightly-coupled memory for instructions and data
• Employs a 6-stage pipeline to achieve maximum DMIPS/MHz
• Performs dynamic branch prediction
• Provides optional hardware multiply, divide, and shift options to improve arithmetic performance
• Supports the addition of custom instructions
• Optional ECC support for internal RAM blocks (instruction cache, MMU TLB, and register file)
• Supports the JTAG debug module
• Supports optional JTAG debug module enhancements, including hardware breakpoints and real-time
trace
The following sections discuss the noteworthy details of the Nios II/f core implementation. This
document does not discuss low-level design issues or implementation details that do not affect Nios II
hardware or software designers.
Arithmetic Logic Unit
The Nios II/f core provides several arithmetic logic unit (ALU) options to improve the performance of
multiply, divide, and shift operations.
Multiply and Divide Performance
The Nios II/f core provides the following hardware multiplier options:
• DSP Block—Includes DSP block multipliers available on the target device. This option is available only
on Altera FPGAs that have DSP Blocks.
• Embedded Multipliers—Includes dedicated embedded multipliers available on the target device. This
option is available only on Altera FPGAs that have embedded multipliers.
• Logic Elements—Includes hardware multipliers built from logic element (LE) resources.
• None—Does not include multiply hardware. In this case, multiply operations are emulated in software.
5-4
Overview
NII51015
2015.04.02
Altera Corporation
Nios II Core Implementation Details
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