Specifications

Feature
Core
Nios II/e Nios II/s Nios II/f
Data Bus
Cache – – 512 bytes to 64 KB
Pipelined Memory
Access
– – –
Cache Bypass Methods – –
• I/O instructions
• Bit-31 cache bypass
• Optional MMU
Tightly-Coupled
Memory
– – Optional
Arithmetic Logic Unit
Hardware Multiply – 3-cycle
(44)
1-cycle
(44)
Hardware Divide – Optional Optional
Shifter 1 cycle-per-bit 3-cycle shift
(44)
1-cycle barrel
shifter
(44)
JTAG Debug Module
JTAG interface, run
control, software
breakpoints
Optional Optional Optional
Hardware Breakpoints – Optional Optional
Off-Chip Trace Buffer – Optional Optional
Memory Management Unit – – Optional
Memory Protection Unit – – Optional
Exception Handling
Exception Types Software trap,
unimplemented
instruction, illegal
instruction, hardware
interrupt
Software trap,
unimplemented
instruction, illegal
instruction,
hardware interrupt
Software trap, unimplemented
instruction, illegal instruction,
supervisor-only instruction,
supervisor-only instruction
address, supervisor-only data
address, misaligned destination
address, misaligned data address,
division error, fast TLB miss,
double TLB miss, TLB permission
violation, MPU region violation,
internal hardware interrupt,
external hardware interrupt,
nonmaskable interrupt
Integrated Interrupt
Controller
Yes Yes Yes
External Interrupt
Controller Interface
No No Optional
Shadow Register Sets No No Optional, up to 63
User Mode Support No; Permanently in
supervisor mode
No; Permanently in
supervisor mode
Yes; When MMU or MPU present
Custom Instruction Support Yes Yes Yes
ECC support No No Yes
(43)
DMIPS performance for the Nios II/s and Nios II/f cores depends on the hardware multiply option.
5-2
Nios II Core Implementation Details
NII51015
2015.04.02
Altera Corporation
Nios II Core Implementation Details
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