Specifications
Nios II Core Implementation Details
5
2015.04.02
NII51015
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This document describes all of the Nios
®
II processor core implementations available at the time of
publishing. This document describes only implementation-specific features of each processor core. All
cores support the Nios II instruction set architecture.
For more information regarding the Nios II instruction set architecture, refer to the Instruction Set
Reference chapter of the Nios II Processor Reference Handbook.
For common core information and details on a specific core, refer to the appropriate section:
Table 5-1: Nios II Processor Cores
Feature
Core
Nios II/e Nios II/s Nios II/f
Objective Minimal core size Small core size Fast execution speed
Performance
DMIPS/MHz
(43)
0.15 0.74 1.16
Max. DMIPS 31 127 218
Max. f
MAX
200 MHz 165 MHz 185 MHz
Area < 700 LEs;
< 350 ALMs
< 1400 LEs;
< 700 ALMs
Without MMU or MPU:
< 1800 LEs;
< 900 ALMs
With MMU:
< 3000 LEs;
< 1500 ALMs
With MPU:
< 2400 LEs;
< 1200 ALMs
Pipeline 1 stage 5 stages 6 stages
External Address Space 2 GB 2 GB 2 GB without MMU
4 GB with MMU
Instruction Bus
Cache – 512 bytes to 64 KB 512 bytes to 64 KB
Pipelined Memory
Access
– Yes Yes
Branch Prediction – Static Dynamic
Tightly-Coupled
Memory
– Optional Optional
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