Specifications

For information about converting SOPC Builder designs to Qsys, refer to the SOPC Builder to Qsys
Migration Guidelines.
Related Information
SOPC Builder to Qsys Migration Guidelines
Floating Point Hardware 2 Custom Instruction
The Nios II processor offers a set of optional predefined custom instructions that implement floating-
point arithmetic operations. You can include these custom instructions to support computation-intensive
floating-point applications.
The Floating Point Hardware 2 Custom Instruction is a high performance component with predefined
custom instructions that implement single-precision floating-point operations. This component offers
improved performance with lower cycle counts for addition, subtraction, multiplication and division, and
also supports floating-point operations such as square root, comparison, minimum/maximum, negate/
absolute, and conversion.
The Floating Point Hardware 2 component is composed of two custom instructions:
• Combinational custom instruction—Implements the minimum, maximum, compare, negate, and
absolute operations.
• Multi-cycle custom instruction—Implements the add, substract, multiply, divide, square root, and
convert operations.
The component has two slaves, one slave for the combinatorial custom instruction and the other slave for
the multi-cycle custom instruction.
The opcode extensions for the Floating Point Hardware 2 custom instructions are 224 through 255. Refer
to the Floating Point Custom Instruction 2 Operation Summary table in the "Floating Point Custom
Instruction 2 Component" section in the Processor Architecture chapter for details.
To add the Floating Point Hardware 2 custom instruction to the Nios II processor in Qsys, select Floating
Point Hardware 2 under Embedded Processors in the Component Library tab. Connect the two slave
interfaces to the Nios II custom instruction master.
Related Information
Floating Point Custom Instruction 2 Component on page 2-8
Floating-Point Hardware Custom Instruction
Floating-Point Hardware Custom Instruction
The Nios II processor offers a set of optional predefined custom instructions that implement floating-
point arithmetic operations. You can include these custom instructions to support computation-intensive
floating-point applications.
The basic set of floating-point custom instructions includes single precision (32-bit) floating-point
addition, subtraction, and multiplication. Floating-point division is available as an extension to the basic
instruction set. The best choice for your hardware design depends on a balance among floating-point
usage, hardware resource usage, and performance.
If the target device includes on-chip multiplier blocks, the floating-point custom instructions incorporate
them as needed. If there are no on-chip multiplier blocks, the floating-point custom instructions are
entirely based on general-purpose logic elements.
Note:
The opcode extensions for the floating-point custom instructions are 252 through 255 (0xFC
through 0xFF). These opcode extensions cannot be modified.
NII51004
2015.04.02
Floating Point Hardware 2 Custom Instruction
4-17
Instantiating the Nios II Processor
Altera Corporation
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