Specifications

Related Information
General Exception Vector on page 4-4
Advanced Debug Settings
Debug levels 3 and 4 support trace data collection into an on-chip memory buffer. You can set the on-
chip trace buffer size to sizes from 128 to 64K trace frames, using OCI Onchip Trace. Larger buffer sizes
consume more on-chip M4K RAM blocks. Every M4K RAM block can store up to 128 trace frames.
Note: The Nios II MMU does not support the JTAG debug module trace.
Debug level 4 also supports manual 2X clock signal specification. If you want to use a specific 2X clock
signal in your FPGA design, turn off Automatically generate internal 2x clock signal and drive a 2X
clock signal into your system manually.
For more information about trace frames, refer to the Processor Architecture chapter of the Nios II
Processor Reference Handbook.
Related Information
• Processor Architecture on page 2-1
• Processor Architecture
Custom Instruction Tab
In Qsys, custom instructions are components in your design that you manually connect to the processor
in the Qsys System Contents tab. Existing custom instruction components are available on the
Component Library tab under Custom Instruction Modules. Thus, the Custom Instruction tab in the
Nios II Processor parameter editor is not used in Qsys.
To create your own custom instruction using the component editor, click New Component on the File
menu in Qsys. After finishing in the component editor, the new instruction appears on the Component
Library tab under Custom Instruction Modules in Qsys.
Note:
All signals in Nios II custom instructions must have the Custom Instruction Slave interface type.
To guarantee the component editor automatically selects the Custom Instruction Slave interface type for
your signals correctly during import, begin your signal names with the prefix ncs_. This prefix allows the
component editor to determine the connection point type: a Nios II custom instruction slave. For
example, if a custom instruction component has two data signals plus clock, reset, and result signals, an
appropriate set of signal names is ncs_dataa, ncs_datab, ncs_clk, ncs_reset, and ncs_result.
A complete discussion of the hardware and software design process for custom instructions is beyond the
scope of this chapter.
For full details on the topic of custom instructions, including working example designs, refer to the Nios II
Custom Instruction User Guide.
Related Information
Nios II Custom Instruction User Guide
Altera-Provided Custom Instructions
The following sections describe the custom instructions Altera provides.
Note:
The Endian Converter Custom Instruction and Interrupt Vector Custom Instruction are not
available in Qsys.
4-16
Advanced Debug Settings
NII51004
2015.04.02
Altera Corporation
Instantiating the Nios II Processor
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