Specifications
Feature Description
Hardware
Breakpoints
Sets a breakpoint on instructions residing in nonvolatile memory, such as flash
memory.
Data Triggers Triggers based on address value, data value, or read or write cycle. You can use a
trigger to halt the processor on specific events or conditions, or to activate other
events, such as starting execution trace, or sending a trigger signal to an external logic
analyzer. Two data triggers can be combined to form a trigger that activates on a
range of data or addresses.
Instruction Trace Captures the sequence of instructions executing on the processor in real time.
Data Trace Captures the addresses and data associated with read and write operations executed
by the processor in real time.
On-Chip Trace Stores trace data in on-chip memory.
Off-Chip Trace Stores trace data in an external debug probe. Off-chip trace instantiates a PLL inside
the Nios II core. Off-chip trace requires a debug probe from Imagination Technolo‐
gies or Lauterbach GmbH.
The following sections describe the configuration settings available.
Related Information
• Advanced Debug Settings on page 4-16
• Break Vector on page 4-15
• Debug Signals on page 4-15
• Debug Level Settings on page 4-14
Debug Level Settings
The following debug levels are available in the JTAG Debug Module tab:
• No Debugger
• Level 1
• Level 2
• Level 3
• Level 4
The table is a detailed list of the characteristics of each debug level. Different levels consume different
amounts of on-chip resources. Certain Nios II cores have restricted debug options, and certain options
require debug tools provided by Imagination Technologies, LLC or Lauterbach GmbH.
Table 4-7: JTAG Debug Module Levels
Debug Feature No Debug Level 1 Level 2 Level 3 Level 4
(39)
Logic Usage 0 300—400
LEs
800—900
LEs
2,400—2,700
LEs
3,100—
3,700 LEs
On-Chip Memory Usage 0 Two M4Ks Two M4Ks Four M4Ks Four M4Ks
External I/O Pins Required
(40)
0 0 0 0 20
JTAG Target Connection No Yes Yes Yes Yes
4-14
Debug Level Settings
NII51004
2015.04.02
Altera Corporation
Instantiating the Nios II Processor
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