Specifications

Because the pins and logic resources in Altera devices are programmable, many customizations are
possible:
• You can rearrange the pins on the chip to simplify the board design. For example, you can move
address and data pins for external SDRAM memory to any side of the chip to shorten board traces.
• You can use extra pins and logic resources on the chip for functions unrelated to the processor. Extra
resources can provide a few extra gates and registers as glue logic for the board design; or extra
resources can implement entire systems. For example, a Nios II processor system consumes only 5% of
a large Altera FPGA, leaving the rest of the chip’s resources available to implement other functions.
• You can use extra pins and logic on the chip to implement additional peripherals for the Nios II
processor system. Altera offers a library of peripherals that easily connect to Nios II processor systems.
Configurable Soft Processor Core Concepts
This section introduces Nios II concepts that are unique or different from other discrete microcontrollers.
The concepts described in this section provide a foundation for understanding the rest of the features
discussed in this handbook.
Configurable Soft Processor Core
The Nios II processor is a configurable soft IP core, as opposed to a fixed, off-the-shelf microcontroller.
You can add or remove features on a system-by-system basis to meet performance or price goals. Soft
means the processor core is not fixed in silicon and can be targeted to any Altera FPGA family.
You are not required to create a new Nios II processor configuration for every new design. Altera provides
ready-made Nios II system designs that you can use as is. If these designs meet your system requirements,
there is no need to configure the design further. In addition, you can use the Nios II instruction set
simulator to begin writing and debugging Nios II applications before the final hardware configuration is
determined.
Flexible Peripheral Set and Address Map
A flexible peripheral set is one of the most notable differences between Nios II processor systems and
fixed microcontrollers. Because the Nios II processor is implemented in programmable logic, you can
easily build made-to-order Nios II processor systems with the exact peripheral set required for the target
applications.
Altera provides software constructs to access memory and peripherals generically, independently of
address location. Therefore, the flexible peripheral set and address map does not affect application
developers.
There are two broad classes of peripherals: standard peripherals and custom peripherals.
Standard Peripherals
Altera provides a set of peripherals commonly used in microcontrollers, such as timers, serial
communication interfaces, general-purpose I/O, SDRAM controllers, and other memory interfaces. The
list of available peripherals continues to increase as Altera and third-party vendors release new
peripherals.
Related Information
Embedded Peripherals IP User Guide
For information about the Altera-provided cores, refer to the Embedded Peripherals IP User Guide.
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Configurable Soft Processor Core Concepts
NII51001
2015.04.02
Altera Corporation
Introduction
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