Specifications

Related Information
• Programming Model on page 3-1
• Programming Model
• Nios II Core Implementation Details on page 5-1
• Nios II Core Implementation Details
JTAG Debug Module Tab
The JTAG Debug Module tab presents settings for configuring the JTAG debug module on the Nios II
processor. You can select the debug features appropriate for your target application.
Table 4-5: JTAG Debug Module Tab Parameters
Name Description
Select a Debugging Level
Debug level Refer to the "Debug Level Settings" section.
Include debugreq and debugack
Signals
Refer to the "Debug Signals" section.
Break Vector
Break vector memory
Refer to the "Break Vector" section.Break vector offset
Break vector
Advanced Debug Settings
OCI Onchip Trace
Refer to "Advanced Debug Settings" section.
Automatically generate internal 2x
clock signal
Soft processor cores such as the Nios II processor offer unique debug capabilities beyond the features of
traditional fixed processors. The soft nature of the Nios II processor allows you to debug a system in
development using a full-featured debug core, and later remove the debug features to conserve logic
resources. For the release version of a product, you might choose to reduce the JTAG debug module
functionality, or remove it altogether.
Table 4-6: Debug Configuration Features
Feature Description
JTAG Target
Connection
Connects to the processor through the standard JTAG pins on the Altera FPGA. This
connection provides the basic capabilities to start and stop the processor, and
examine/edit registers and memory.
Download
Software
Downloads executable code to the processor’s memory via the JTAG connection.
Software
Breakpoints
Sets a breakpoint on instructions residing in RAM.
NII51004
2015.04.02
JTAG Debug Module Tab
4-13
Instantiating the Nios II Processor
Altera Corporation
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