Specifications

MMU
When Include MMU on the Core Nios II tab is on, the MMU settings on the MMU and MPU Settings
tab provide the following options for the MMU in the Nios II/f core. Typically, you should not need to
change any of these settings from their default values.
• Process ID (PID) bits—Specifies the number of bits to use to represent the process identifier.
• Optimize number of TLB entries based on device family—When on, specifies the optimal number of
TLB entries to allocate based on the device family of the target hardware and disables TLB entries.
• TLB entries—Specifies the number of entries in the translation lookaside buffer (TLB).
• TLB Set-Associativity—Specifies the number of set-associativity ways in the TLB.
• Micro DTLB entries—Specifies the number of entries in the micro data TLB.
• Micro ITLB entries—Specifies the number of entries in the micro instruction TLB.
For information about the MMU, refer to the Programming Model chapter of the Nios II Processor
Reference Handbook.
For specifics on the Nios II/f core, refer to the Nios II Core Implementation Details chapter of the Nios II
Processor Reference Handbook.
Related Information
• Programming Model on page 3-1
• Programming Model
• Nios II Core Implementation Details on page 5-1
• Nios II Core Implementation Details
MPU
When Include MPU on the Core Nios II tab is on, the MPU settings on the MMU and MPU Settings tab
provide the following options for the MPU in the Nios II/f core.
• Use Limit for region range—Controls whether the amount of memory in the region is defined by size
or by upper address limit. When on, the amount of memory is based on the given upper address limit.
When off, the amount of memory is based on the given size.
• Number of data regions—Specifies the number of data regions to allocate. Allowed values range from
2 to 32.
• Minimum data region size—Specifies the minimum data region size. Allowed values range from
64 bytes to 1 MB and must be a power of two.
• Number of instruction regions—Specifies the number of instruction regions to allocate. Allowed
values range from 2 to 32.
• Minimum instruction region size—Specifies the minimum instruction region size. Allowed values
range from 64 bytes to 1 MB and must be a power of two.
Note:
The maximum region size is the size of the Nios II instruction and data addresses automatically
determined when the Nios II system is generated in Qsys. Maximum region size is based on the
address range of slaves connected to the Nios II instruction and data masters.
For information about the MPU, refer to the Programming Model chapter of the Nios II Processor
Reference Handbook.
For specifics on the Nios II/f core, refer to the Nios II Core Implementation Details chapter of the Nios II
Processor Reference Handbook.
4-12
MMU
NII51004
2015.04.02
Altera Corporation
Instantiating the Nios II Processor
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