Specifications

Related Information
Altera ASICs
ECC
ECC is only available for the Nios II/f core and provides ECC support for Nios II internal RAM blocks,
such as instruction cache, MMU TLB, and register file. The SECDED ECC algorithm is based on
Hamming codes, which detect 1 or 2 bit errors and corrects 1 bit errors. If the Nios II processor does not
attempt to correct any errors and only detects them, the ECC algorithm can detect 3 bit errors.
Refer to "ECC" section in the Nios II Core Implementation Details chapter for more information about
ECC support in the Nios II/f core.
Related Information
• Nios II Core Implementation Details on page 5-1
• Nios II Core Implementation Details
MMU and MPU Settings Tab
The MMU and MPU Settings tab presents settings for configuring the MMU and MPU on the Nios II
processor. You can select the features appropriate for your target application.
Table 4-4: MMU and MPU Settings Tab Parameters
Name Description
MMU
Process ID (PID) bits
Refer to the "MMU" section.
Optimize number of TLB entries based
on device family
TLB entries
TLB Set-Associativity
Micro DTLB entries
Micro ITLB entries
MPU
Use Limit for region range
Refer to the "MPU" section.
Number of data regions
Minimum data region size
Number of instruction regions
Minimum instruction region size
Related Information
• MPU on page 4-12
• MMU on page 4-12
NII51004
2015.04.02
ECC
4-11
Instantiating the Nios II Processor
Altera Corporation
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