Specifications

Related Information
SOPC Builder to Qsys Migration Guidelines
For information about upgrading IDs that were manually-assigned values in Qsys, refer to the SOPC
Builder to Qsys Migration Guideline.
Exception Checking
The Exception Checking settings provide the following options:
• Illegal instruction—When Illegal instruction is on, the processor generates an illegal instruction
exception when an instruction with an undefined opcode or opcode-extension field is executed.
Note: When your system contains an MMU or MPU, the processor automatically generates illegal
instruction exceptions. Therefore, the Illegal instruction setting is always disabled when the Core
Nios II tab Include MMU or Include MPU are on.
• Division error—Division error detection is only available for the Nios II/f core, and only then when
Hardware divide on the Core Nios II tab is on. When divide instructions are not supported by
hardware, the Division error setting is disabled.
When Division error is on, the processor generates a division error exception when it detects divide
instructions that produce a result that cannot be represented in the destination register. This only
happens in the following two cases:
• Divide by zero
• Divide overflow—A signed division that divides the largest negative number -2147483648
(0x80000000) by -1 (0xffffffff).
• Misaligned memory access—Misaligned memory access detection is only available for the Nios II/f
core. When Misaligned memory access is on, the processor checks for misaligned memory accesses.
Note:
When your system contains an MMU or MPU, the processor automatically generates misaligned
memory access exceptions. Therefore, the Misaligned memory access check box is always disabled
when Include MMU or Include MPU on the Core Nios II tab are on.
There are two misaligned memory address exceptions:
• Misaligned data address—Data addresses of load and store instructions are checked for misalignment.
A data address is considered misaligned if the byte address is not a multiple of the data width of the
load or store instruction (4 bytes for word, 2 bytes for half-word). Byte load and store instructions are
always aligned so never generate a misaligned data address exception.
• Misaligned destination address—Destination instruction addresses of br, callr, jmp, ret, eret, and
bret instructions are checked for misalignment. A destination instruction address is considered
misaligned if the target byte address of the instruction is not a multiple of four.
• Extra exception information—When Extra exception information is on, nonbreak exceptions store a
code in the CAUSE field of the exception control register to indicate the cause of the exception.
Note:
When your system contains an MMU or MPU, the processor automatically generates extra
exception information. Therefore, the Extra exception information setting is always disabled
when the Core Nios II tab Include MMU or Include MPU are on.
Your exception handler can use this code to quickly determine the proper action to take, rather than have
to determine the cause of an exception through instruction decoding. Additionally, some exceptions also
store the instruction or data address associated with the exception in the badaddr register.
For further descriptions of exceptions, exception handling, and control registers, refer to the Program‐
ming Model chapter of the Nios II Processor Reference Handbook.
NII51004
2015.04.02
Exception Checking
4-9
Instantiating the Nios II Processor
Altera Corporation
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