Specifications

Name Description
Illegal instruction
Refer to the "Exception Checking" section.
Division error
Misaligned memory access
Extra exception information
HardCopy Compatibility
HardCopy compatible Refer to the "Hardcopy Compatible" section.
ECC
ECC present Refer to the "ECC" section.
Related Information
• ECC on page 4-11
• HardCopy Compatible on page 4-10
• Exception Checking on page 4-9
• Control Registers on page 4-8
• Reset Signals on page 4-8
• Shadow Register Sets on page 4-10
• Interrupt Controller Interfaces on page 4-10
Reset Signals
The Include cpu_resetrequest and cpu_resettaken signals reset signals setting provides the following
functionality. When on, the Nios II processor includes processor-only reset request signals. These signals
let another device individually reset the Nios II processor without resetting the entire system. The signals
are exported to the top level of your system.
Note:
You must manually connect these signals to logic external to your Qsys system.
For more information on the reset signals, refer to the Processor Architecture chapter of the Nios II
Processor Reference Handbook.
Related Information
• Processor Architecture on page 2-1
• Processor Architecture
Control Registers
The Assign cpuid control register value manually control register setting allows you to assign the cpuid
control register value yourself. In Qsys, the automatically-assigned value is always 0x00000000, so Altera
recommends always assigning the value manually.
To assign the value yourself, turn on Assign cpuid control register value manually and type a 32-bit
value (in hexadecimal or decimal format) in the cpuid control register value box.
4-8
Reset Signals
NII51004
2015.04.02
Altera Corporation
Instantiating the Nios II Processor
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