Specifications

Data Master Settings
The Data Master parameters provide the following options for the Nios II/f core:
• Omit data master port—Removes the Avalon-MM data master port from the Nios II processor. The
port is only successfully removed when Data cache is set to None and Number of tightly coupled
data master port(s) is greater than zero.
Note: Although the Nios II processor can operate entirely out of tightly-coupled memory without the
need for Avalon-MM instruction or data masters, software debug is not possible when either the
Avalon-MM instruction or data master is omitted.
• Data cache—Specifies the size of the data cache. Valid sizes are from 512 bytes to 64 KBytes, or None.
Depending on the value specified for Data cache, the following options are available:
• Data cache line size—Valid sizes are 4 bytes, 16 bytes, or 32 bytes.
• Burst transfers —The Nios II processor can fill its data cache lines using burst transfers. Usually
you enable bursts on the processor's data bus when processor data is stored in DRAM, and disable
bursts when processor data is stored in SRAM.
Bursting to DRAM typically improves memory bandwidth but might consume additional FPGA
resources. Be aware that when bursts are enabled, accesses to slaves might go through additional
hardware (called burst adapters) which might decrease your f
MAX
.
Bursting is only enabled for data cache line sizes greater than 4 bytes. The burst length is 4 for a 16
byte line size and 8 for a 32 byte line size. Data cache bursts are always aligned on the cache line
boundary. For example, with a 32-byte Nios II data cache line, a cache miss to the address 8 results
in a burst with the following address sequence: 0, 4, 8, 12, 16, 20, 24 and 28.
• Number of tightly coupled data master port(s) (Include tightly coupled data master port(s))—
Specifies one to four tightly-coupled data master ports for the Nios II processor. In Qsys, select the
number from the Number of tightly coupled data master port(s) list. Tightly-coupled memory ports
appear on the connection panel of the Nios II processor on the Qsys System Contents tab. You must
connect each port to exactly one memory component in the system.
Advanced Features Tab
The Advanced Features tab allows you to enable specialized features of the Nios II processor.
Table 4-3: Advanced Features Tab Parameters
Name Description
General
Interrupt controller Refer to the "Interrupt Controller" Interfaces section.
Number of shadow register sets Refer to the "Shadow Register Sets" section.
Include cpu_resetrequest and cpu_
resettaken signals
Refer to the "Reset Signal"s section.
Assign cpuid control register value
manually
Refer to the "Control Registers" section.
cpuid control register value
Exception Checking
NII51004
2015.04.02
Data Master Settings
4-7
Instantiating the Nios II Processor
Altera Corporation
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