Specifications

Note: The Nios II MMU is optional and mutually exclusive from the Nios II MPU. Nios II systems can
include either an MMU or MPU, but cannot include both an MMU and MPU in the same design.
For information about the Nios II MMU, refer to the Programming Model chapter of the Nios II Processor
Reference Handbook.
To function correctly with the MMU, the base physical address of all exception vectors (reset, general
exception, break, and fast TLB miss) must point to low physical memory so that hardware can correctly
map their virtual addresses into the kernel partition. This restriction is enforced by the Nios II Processor
parameter editor.
Related Information
• Programming Model on page 3-1
• Programming Model
Memory Protection Unit Settings
The Nios II/f core offers a memory protection unit (MPU) to support operating systems and runtime
environments that desire memory protection without the overhead of virtual memory management.
Turning on Include MPU includes the Nios II MPU in your Nios II hardware system.
Note:
The Nios II MPU is optional and mutually exclusive from the Nios II MMU. Nios II systems can
include either an MPU or MMU, but cannot include both an MPU and MMU in the same design.
For information about the Nios II MPU, refer to the Programming Model chapter of the Nios II Processor
Reference Handbook.
Related Information
• Programming Model on page 3-1
• Programming Model
Caches and Memory Interfaces Tab
The Caches and Memory Interfaces tab allows you to configure the cache and tightly-coupled memory
usage for the instruction and data master ports.
Table 4-2: Caches and Memory Interfaces Tab Parameters
Name Description
Instruction Master
Instruction cache
Refer to the "Instruction Master Settings" Section.
Burst transfers
Number of tightly coupled instruction
master port(s)
Data Master
NII51004
2015.04.02
Memory Protection Unit Settings
4-5
Instantiating the Nios II Processor
Altera Corporation
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