Specifications

General Exception Vector
Parameters in this section select the memory module where the general exception vector (exception
address) resides, and the location of the general exception vector. The general exception vector cannot be
configured until your system memory components are in place.
The Exception vector memory list, which includes all memory modules mastered by the Nios II
processor, selects the exception vector memory module. In a typical system, select a low-latency memory
module for the exception code.
Note: Qsys provides an Absolute option, which allows you to specify an absolute address in Exception
vector offset. Use an absolute address when the memory storing the exception handler is located
outside of the processor system and subsystems of the processor system.
Exception vector offset specifies the location of the exception vector relative to the memory module’s
base address. Qsys calculates the physical address of the exception vector when you modify the memory
module, the offset, or the memory module’s base address. In Qsys, Exception vector displays the read-
only, calculated address.. The address is always a physical address, even when an MMU is present.
For information about exceptions, refer to the Programming Model chapter of the Nios II Processor
Reference Handbook.
Related Information
• Programming Model on page 3-1
• Programming Model
Memory Management Unit Settings
The Nios II/f core offers a memory management unit (MMU) to support full-featured operating systems.
Turning on Include MMU includes the Nios II MMU in your Nios II hardware system.
Note:
Do not include an MMU in your Nios II system unless your operating system requires it. The
MMU is only useful with software that takes advantage of it. Many Nios II systems involve simpler
system software, such as Altera HAL or MicroC/OS-II. Such software is unlikely to function
correctly with an MMU-based Nios II processor.
Fast TLB Miss Exception Vector
The fast TLB miss exception vector is a special exception vector used exclusively by the MMU to handle
TLB miss exceptions. Parameters in this section select the memory module where the fast TLB miss
exception vector (exception address) resides, and the location of the fast TLB miss exception vector. The
fast TLB miss exception vector cannot be configured until your system memory components are in place.
The Fast TLB Miss Exception vector memory list, which includes all memory modules mastered by the
Nios II processor, selects the exception vector memory module. In a typical system, select a low-latency
memory module for the exception code.
Note:
Qsys provides an Absolute option, which allows you to specify an absolute address in Fast TLB
Miss Exception vector offset. Use an absolute address when the memory storing the exception
handler is located outside of the processor system and subsystems of the processor system.
Fast TLB Miss Exception vector offset specifies the location of the exception vector relative to the memory
module’s base address. Qsys calculates the physical address of the exception vector when you modify the
memory module, the offset, or the memory module’s base address. In Qsys, Fast TLB Miss Exception
vector displays the readonly, calculated address. The address is always a physical address, even when an
MMU is present.
4-4
General Exception Vector
NII51004
2015.04.02
Altera Corporation
Instantiating the Nios II Processor
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