Specifications

Figure 1-1: Example of a Nios II Processor System
Nios II
Processor Core
SDRAM
Controller
On-Chip ROM
Tristate bridge to
off-chip memory
System Interconnect Fabric
JTAG
Debug Module
SDRAM
Memory
Flash
Memory
SRAM
Memory
UART
Timer1
Timer2
LCD Display Driver
General-Purpose I/O
Ethernet Interface
CompactFlash
Interface
LCD
Screen
Ethernet
MAC/PHY
Compact
Flash
Buttons,
LEDs, etc.
TXD
RXD
JTAG connection
to software debugger
Clock
Reset
Data
Inst.
If the prototype system adequately meets design requirements using an Altera-provided reference design,
you can copy the reference design and use it without modification in the final hardware platform.
Otherwise, you can customize the Nios II processor system until it meets cost or performance require‐
ments.
Related Information
All Development Kits
For a list of available development kits, refer to the All Development Kits page of the Altera website.
Customizing Nios II Processor Designs
In practice, most FPGA designs implement some extra logic in addition to the processor system. Altera
FPGAs provide flexibility to add features and enhance performance of the Nios II processor system. You
can also eliminate unnecessary processor features and peripherals to fit the design in a smaller, lower-cost
device.
NII51001
2015.04.02
Customizing Nios II Processor Designs
1-3
Introduction
Altera Corporation
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