Specifications

Multiply and Divide Settings
The Nios II/s and Nios II/f cores offer hardware multiply and divide options. You can choose the best
option to balance embedded multiplier usage, logic element (LE) usage, and performance.
The Hardware multiplication type parameter for each core provides the following list:
• DSP Block—Include DSP block multipliers in the arithmetic logic unit (ALU). This option is only
selectable when targeting devices that have DSP block multipliers.
• Embedded Multipliers—Include embedded multipliers in the ALU. This option is only present when
targeting FPGA devices that have embedded multipliers.
• Logic Elements—Include LE-based multipliers in the ALU. This option achieves high multiply
performance without consuming embedded multiplier resources, but with reduced f
MAX
.
• None—This option conserves logic resources by eliminating multiply hardware. Multiply operations
are implemented in software.
Note:
Shift operations use the multiplier. So, Hardware multiplication type affects shift instruction
speed.
Turning on Hardware divide includes LE-based divide hardware in the ALU. The Hardware divide
option achieves much greater performance than software emulation of divide operations.
For information about the performance effects of the hardware multiply and divide options, refer to the
Nios II Core Implementation Details chapter of the Nios II Processor Reference Handbook.
Related Information
• Nios II Core Implementation Details on page 5-1
• Nios II Core Implementation Details
Reset Vector
Parameters in this section select the memory module where the reset code (boot loader) resides, and the
location of the reset vector (reset address). The reset vector cannot be configured until your system
memory components are in place.
The Reset vector memory list, which includes all memory modules mastered by the Nios II processor,
selects the reset vector memory module. In a typical system, select a nonvolatile memory module for the
reset code.
Note:
Qsys provides an Absolute option, which allows you to specify an absolute address in Reset vector
offset. Use an absolute address when the memory storing the reset handler is located outside of the
processor system and subsystems of the processor system.
Reset vector offset specifies the location of the reset vector relative to the memory module’s base address.
Qsys calculates the physical address of the reset vector when you modify the memory module, the offset,
or the memory module’s base address. In Qsys, Reset vector displays the read-only, calculated address.
The address is always a physical address, even when an MMU is present.
For information about reset exceptions, refer to the Programming Model chapter of the Nios II Processor
Reference Handbook.
Related Information
• Programming Model on page 3-1
• Programming Model
NII51004
2015.04.02
Multiply and Divide Settings
4-3
Instantiating the Nios II Processor
Altera Corporation
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