Specifications

Name Description
Exception Vector
Exception vector memory
Refer to the "General Exception Vectors" section.Exception vector offset
Exception vector
MMU and MPU
Include MMU
Refer to the "Memory Management Unit Settings" section.
Fast TLB Miss Exception vector
memory
Fast TLB Miss Exception vector offset
Fast TLB Miss Exception vector
Include MPU Refer to the "Memory Protection Unit Settings" section.
The following sections describe the configuration settings available.
Related Information
• Memory Management Unit Settings on page 4-4
• General Exception Vector on page 4-4
• Multiply and Divide Settings on page 4-3
• Reset Vector on page 4-3
• Core Selection on page 4-2
• Memory Protection Unit Settings on page 4-5
Core Selection
The main purpose of the Core Nios II tab is to select the processor core. The core you select on this tab
affects other options available on this and other tabs.
Altera offers the following Nios II cores:
• Nios II/f—The Nios II/f fast core is designed for fast performance. As a result, this core presents the
most configuration options allowing you to fine tune the processor for performance.
• Nios II/s—The Nios II/s standard core is designed for small size while maintaining performance.
• Nios II/e—The Nios II/e economy core is designed to achieve the smallest possible core size. As a
result, this core has a limited feature set, and many settings are not available when the Nios II/e core is
selected.
The Core Nios II tab displays a selector guide table that lists the basic properties of each core.
For implementation information about each core, refer to the Nios II Core Implementation Details chapter
of the Nios II Processor Reference Handbook.
Related Information
• Nios II Core Implementation Details on page 5-1
• Nios II Core Implementation Details
4-2
Core Selection
NII51004
2015.04.02
Altera Corporation
Instantiating the Nios II Processor
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