User guide

© 2010 Ingenieurbüro Für Ic-Technologie Page 59
Details DMA
the GMACII includes an internal DMA controller with special features:
 alignment aware and byte exact
the GMACII-DMA is able to copy an exact number of bytes from the source (byteaddress) to the destination
(byteaddress), with this feature we get the high copy-performance of up to 4 Bytes/clk_cycle even when the
databytes need to be shifted 1,2 or 3 bytes (limitation: we read some bytes more than we need)
 checksum logic
all written bytes are going into the checksum-adder, so after each copying is done the checksum can be
read, there is no overhead, when not used, the checksum-adder is cleared with each new copy request,
the receive part and the transmit part have their own checksum registers.
 pipelinesupport
the GMACII-DMA has pipeline support on both ends, that means we can reach the maximum possible
throughput
 separate register for receiver and transmitter
we have separate registers for the receiver part of the DMA (reading data from the receive-buffer, writing to
the avalon-bus) and the transmitter part of the DMA (reading from the avalon-bus, writing to the transmit-
buffer), this give better performance, and less overhead
the receiver-DMA can only read the receive-buffer !
the transmit-DMA can only write the transmit-buffer !