User guide

© 2010 Ingenieurbüro Für Ic-Technologie Page 42
Assumptions
 Depending on the used PHY Interface
 You have to provide a 125MHz Clock
− This 125MHz clock is required in 100Mb and 1Gb mode
− Use a PLL within the device
− The external oscillator has to be better than 100ppm
frequency deviation
− An example of this can be found in the reference designs
 For the RGMII interface you have to provide an
additional 125MHz Clock with a 90° Degrees shift