User guide

© 2010 Ingenieurbüro Für Ic-Technologie Page 39
Port description
Portname Direction Usage Description
clk125 input
External
125 MHz clock
TX_CLK input External TX Clock from PHY
RX_CRS input
External
RX_CRS from PHY
RX_COL input
External
RX_COL from PHY
RX_CLK input External RX Clock from PHY
RX_DV input
External
RX_DV from PHY
RX_ER input
External
RX_ER from the PHY
RXD[7..0] input External RXD from the PHY
TX_EN
output External
TX_EN to the PHY
TX_ER
output External
TX_ER to the PHY
TXD[7..0]
output External
TXD to the PHY
PHY_INTRn
input External
Interrupt input (low active)
DUPLEX
bidir External Connect to PHY (optional)
PHYADO
bidir External Connect to PHY (optional)
ANEN
bidir External Connect to PHY (optional)
MDC
output External Connect to PHY
MDIO bidir External Connect to PHY