IFI Nios®II GMACII User Guide © 2004 Altera Corporation Core Version: Document Version: Document Date: 2009.09 2010.01 rev 9.
IFI GMACII High Performance Gigabit Ethernet MAC − Up to 114 MByte/s UDP Data Easily integrated into Nios II systems using SOPC Builder Avalon interface for Nios II processor Independent clock domains for Nios II and GMACII Royalty free Reference Software shipped with IP Verified on Nios II development boards Gigabit Ethernet Phy module available − (only from www.devboards.
IFI GMACII Jumboframe support ( compiletime parameter ) − Receivebuffer 4 (standard),8,16,32,64 or 128 kByte (ringbuffer) − Transmitbuffer 2*2 (standard), 2*4, 2*8, 2*16, 2*32, 2*64 kByte (double buffer) Transmitbuffer-Readback for easy software debugging Automatic frameextension to meet the 64Bytes minimum frame length Multicast support with separate MAC_ID and IP filters IGMP filter All filters can be switched off DMA masteraddress support for no increment Statusbits receivebuffer over
Contents Overview Install Integrating the Core using SOPC Builder Reference Designs Using the Core without Nios Necessary Assignments Detailed Information Ethernet Background Revision History License Agreement © 2004 Altera Corporation
Overview Brief Description Suitable Applications Block Diagram Feature List Altera Implementation Contacting Technical Support © 2004 Altera Corporation
Brief Description IFI_GMACII − This IP combines the advantages of the softwareflexibility with the high performance of a hardware solution Advantages: medium size, software controlled, high performance © 2010 Ingenieurbüro Für Ic-Technologie Page 6
Suitable Applications for GMACII DATA, for example Measurement Systems Data Throughput GMACII ALTERA Device Up to 114 MByte/s Data Throughput PC System Video Up to 114 MByte/s GMACII ALTERA Device Data Throughput Up to 114 MByte/s © 2010 Ingenieurbüro Für Ic-Technologie Page 7 PC System GMACII ALTERA Device DATA, for example printer GMACII ALTERA Device Video
Not Suitable Applications for GMACII PC System PC System GMACII ALTERA Device as Switch or HUB © 2010 Ingenieurbüro Für Ic-Technologie Page 8 PC System PC System
Block Diagram Nios®II Avalon Interconnect Master Slave DMA Avalon Interconnect Slave MAC IFI_PHY_Manager Management ARP ICMP UDP/IP TCP/IP Filter GMACII Interface External DPRAM GMII / MII RGMII Buffer Buffer GMACII User Interface Data © 2010 Ingenieurbüro Für Ic-Technologie Page 9 Ethernet CAT5 RMII DBGIG1 or user PHY DBGIG1 100BASE-TX 1000BASE-T Full duplex
IFI GMACII Feature List 1000 Base-T − Full duplex 100 Base-TX − Full duplex Filter − MAC ID − MAC IP Integrated DMA controller − uses pipeling on both ends − generates checksum on the fly − alignment aware IFI_PHY_Manager included Standard buffers With buffers for jumbo frames Transmitbuffer Transmitbuffer Receivebuffer Receivebuffer − Double buffer − 2000 Byte each − checksum advance logic − Ring buffer − 4 kByte total © 2010 Ingenieurbüro Für Ic-Technologie Page 10 − Dou
IFI GMACII Implementation Design Flows supported − SOPC Builder − Encrypted VHDL Software examples Device families supported − all CYCLONE, STRATIX and ARRIA families Device resource utilization − about 3000 LEs for CYCLONEIII − RAM: 8 M9K Blocks (standard buffers) © 2010 Ingenieurbüro Für Ic-Technologie Page 11
OpenCore Plus Feature Evaluate the IFI GMACII on your board or the Altera Nios II development boards − Stand alone evaluation times out after ~1 hour − If there is a connection between the device and the Quartus programmer the evaluation time is unlimited.
IFI GMACII Reference Design CycloneII 2C35 Development Board Reference Design − With GMII Interface − For the DBGIG1 Gigabit Ethernet Phy Module National Semiconductor DP83865 GigPhy 100Mb/Gigabit capability More information: www.devboards.de DBC3C40 Development Board Reference Design − With RMII Interface − For 2 National Semiconductor DP83848 Phyter (100 Mb) More information: www.devboards.
IFI GMACII Reference Design IFI_GMACII © 2010 Ingenieurbüro Für Ic-Technologie Page 14
IFI GMACII Reference Design External DPRAM This example is included as source code It can be used as starting point for the user data interface © 2010 Ingenieurbüro Für Ic-Technologie Page 15
IFI GMACII Pricing Encrypted Netlist node locked: 5000 EURO Encrypted Netlist Floating License: 6250 EURO Additional node locked (same location) − License: 1250 EURO 1 year maintenance included Maintenance: 10 % from the netlist-price / year Licensing: − Unlimited T-Guard License − Multiproject − Royalty Free © 2010 Ingenieurbüro Für Ic-Technologie Page 16
IFI GMACII Verification Hardware Tested on − Cyclone/II/III Nios II Development Kits − StratixII Nios II Development Kit − DBC2C20/DBC3C40 Cyclone Development Boards Tested with different PHYs − − − − − National Semiconductor DP83865 GigPhy (100 Mb/Gigabit) National Semiconductor DP83847 DsPhyter (100 Mb) National Semiconductor DP83848 Phyter (100 Mb) National Semiconductor DP83640 Phyter (100 Mb) Marvell 88E1111 (100 Mb/Gigabit) © 2010 Ingenieurbüro Für Ic-Technologie Page 17
Contacting Technical Support Although we have made every effort to ensure that this SOPC Builder Ready OpenCore Package works correctly, there might be problems that we have not encountered. For questions about the core's features, functionality, and parameter settings please contact: IFI Ingenieurbüro Für Ic-Technologie P. Riekert & F. Sprenger Kleiner Weg 3 -- 97877 Wertheim -- Germany Phone: (+49)9342/96080 E-Mail: ifi@ifi-pld.de http://www.ifi-pld.
Install How to install SOPC Builder Ready OpenCore Package Software Examples Installation Install the Driver Library Licensing Set up Licensing © 2004 Altera Corporation
Install the IFI GMACII Before you can start using Altera IFI GMACII functions, you must install the IFI GMACII files on your computer. The following instructions describe this process for the IFI GMACII. Close Quartus and IDE. The installed QuartusII version must be 9.1 or newer Install the IFI GMACII Files − The following instructions describe how you install IFI GMACII on computers running the Windows operating system.
SOPC Builder Ready OpenCore Package The SOPC Builder Ready OpenCore Package contains all files required for plug-and-play integration of this core into Altera's SOPC Builder tool, allowing the user to easily evaluate the core within his Avalon-based system.
Licensing OpenCorePlus License This package is shipped with a OpenCorePlus license, \license\license_GMACII_OCP.dat. When the FEATURE line from this license is appended to the user's Quartus II license file, the encrypted VHD file can be read into Quartus II and place and route can be performed. The license permit generation of _time_limited.sof files.
Set Up Licensing To install your license, you can either append the license to your license.dat file or you can specify the IFI GMACII ’s license_GMACII_ocp.dat file in the Quartus II software. − Before you set up licensing for the IFI NIOSII GMACII , you must already have the Quartus II software installed on your computer with licensing set up. Append the License to Your license.dat File − − − − − − To append the license, follow these steps: Open the IFI GMACII license file in a text editor.
Integrating the Core using SOPC Builder Prerequisites Adding the Core to your System Using IPToolBench About Documentation Add/Update Component © 2004 Altera Corporation
Integrating the Core with your System using SOPC Builder This section contains instructions on the following: − Adding the Core to your System − Running the Reference Design These instructions assume that the user is familiar with the − Altera OpenCore evaluation process, − Altera's Quartus II development software, − and the Altera SOPC Builder tool. For more information on these prerequisites, please visit www.altera.com.
Adding the Core to your System This walkthrough involves the following steps: − − − Create a New Quartus II Project Create a New SOPC Builder Design Launch IP Toolbench Step 1: Generate Create a New Quartus II Project − − − − − − − − − − − − − − − Before you begin, you must create a new Quartus II project. With the New Project wizard, you specify the working directory for the project, assign the project name, and designate the name of the top-level design entity.
Adding the Core to your SOPC System Launch SOPC Builder from Quartus II (Tools menu). Select the core by clicking on the core name Click "Add" to add the core to your system.
Info + Documentation Parameters Information © 2010 Ingenieurbüro Für Ic-Technologie Page 28
© 2010 Ingenieurbüro Für Ic-Technologie Page 29
Selected system frequency Transmit Buffer Readback for easy software debugging(yes/no) Dualport RAM Interface(yes/no) Advanced Features(yes/no) Receive Buffer Size(Ringbuffer) Transmit Buffer Size(Doublebuffer) PHY Interface(GMII/MII, MII, RGMII, RMII) PHY speed(100/1000, 100, 1000) Show the PHY support pins (yes/no) © 2010 Ingenieurbüro Für Ic-Technologie Page 30 External PHY Timing Use DEFAULT/USER_DEFINED) Setup time in ns Hold time in ns Maximum Tco in ns Minimum Tco in ns
Adding the Core to your System Specify desired instance name, base address, and IRQ. Connect your Avalon interfaces as necessary Add additional components as required by your design. Complete system generation as described in the Altera SOPC Builder documentation.
Reference Designs Running a Reference Design Creating a Software Project Run a Hardware Configuration © 2004 Altera Corporation
Running a Reference Design Start Quartus II, version 9.0 or higher. Open the Quartus II project \ reference_designs\xxx\IFI_GMACII_Reference_design.qpf Launch SOPC Builder from Quartus II (Tools menu). The Nios CPU has been parameterized and added to the system for you, as have the program and data memories, JTAG_UART and the core itself.
SOPC Connections © 2010 Ingenieurbüro Für Ic-Technologie Page 34 GMACII_master is master for − − − − − onchip_memory_DPRAM_64k slave s2 onchip_memory_DPRAM_4k slave s2 sdram slave ext_ram_bus slave dpram_slave GMACII_slave is mastered by CPU data_master dpram_slave is mastered by GMACII_master
Running a Reference Design Click "Generate" to generate the HDL files. Click "Exit" to go back to Quartus and compile the design. Launch the IDE for creation of software projects or InstructionSetSimulation.
Creating a Software Project File New Project − Select C/C++ Application − Click Next Select the PTF of your project Select Project Template Click on Finish © 2010 Ingenieurbüro Für Ic-Technologie Page 36
Syslib Settings Change the memory settings to any wished RAM which is big enough and fast enough © 2010 Ingenieurbüro Für Ic-Technologie Page 37
Run a Hardware Configuration Select your Project within the C/C++ Projects View Run Run..
Port description Portname Direction Usage Description clk125 input External 125 MHz clock TX_CLK input External TX Clock from PHY RX_CRS input External RX_CRS from PHY RX_COL input External RX_COL from PHY RX_CLK input External RX Clock from PHY RX_DV input External RX_DV from PHY RX_ER input External RX_ER from the PHY RXD[7..0] input External RXD from the PHY TX_EN output External TX_EN to the PHY TX_ER output External TX_ER to the PHY TXD[7..
Port description Portname Direction Usage Description xreaddata[31..0] input External External DPRAM readdata xreaddatavalid input External External DPRAM readdatavalid xwaitrequest input External External DPRAM waitrequest xaddress[17..0] output External External DPRAM address xbyteenable[3..
Necessary Assignments Assumptions © 2004 Altera Corporation
Assumptions Depending on the used PHY Interface You have to provide a 125MHz Clock − This 125MHz clock is required in 100Mb and 1Gb mode − Use a PLL within the device − The external oscillator has to be better than 100ppm frequency deviation − An example of this can be found in the reference designs For the RGMII interface you have to provide an additional 125MHz Clock with a 90° Degrees shift © 2010 Ingenieurbüro Für Ic-Technologie Page 42
Necessary Assignments The necessary timing assignments are automatically written in SDC files for you. You have to provide a user SDC file which contains the clock settings for the system You have to activate TimeQuest Timing analysis and to add your user SDC as the first file and than the automatically generated ifi_gmacii_xxxxx.sdc files.
Detailed Information Address map standard buffers Address map jumbo buffers Registers DMA Transmitter Filters Reference software Reference software flow © 2004 Altera Corporation
Address map 1 standard buffers byte address dword address register name 0x00000000 0x00000000 Receive Count 0x00000004 0x00000001 Receive Buffer 0x00002000 0x00000800 Transmit Buffer 0x00003F70 0x00000FDC TBD checksum 0x00003F74 0x00000FDD TCP/IP checksum 0x00003F78 0x00000FDE UDP/IP checksum 0x00003F7C 0x00000FDF IP checksum 0x00003F80 0x00000FE0 MAC ID low 0x00003F84 0x00000FE1 MAC ID high 0x00003F88 0x00000FE2 MAC IP 0x00003F8C 0x00000FE3 Command/Status/IFG 0x00003F90
Address map 2 standard buffers byte address dword address register name 0x00003FC0 0x00000FF0 DMA Control 0x00003FC4 0x00000FF1 Receive Destination (avalon) 0x00003FC8 0x00000FF2 Receive Source GMACII 0x00003FCC 0x00000FF3 Receive Length 0x00003FD0 0x00000FF4 Receive Checksum 0x00003FD4 0x00000FF5 Transmit Source (avalon) 0x00003FD8 0x00000FF6 Transmit Destination GMACII 0x00003FDC 0x00000FF7 Transmit Length 0x00003FE0 0x00000FF8 Transmit Checksum 0x00003FE4 0x00000FF9 Timer
Address map 1 Advanced Features ON byte address dword address register name 0x00000000 0x00000000 Receive Count 0x00000004 0x00000001 Receive Buffer 0x00010000 0x00004000 Transmit Buffer 0x0001FF70 0x00007FDC TBD checksum 0x0001FF74 0x00007FDD TCP/IP checksum 0x0001FF78 0x00007FDE UDP/IP checksum 0x0001FF7C 0x00007FDF IP checksum 0x0001FF80 0x00007FE0 MAC ID low 0x0001FF84 0x00007FE1 MAC ID high 0x0001FF88 0x00007FE2 MAC IP 0x0001FF8C 0x00007FE3 Command/Status/IFG 0x0001F
Address map 2 Advanced Features ON byte address dword address register name 0x0001FFA4 0x00007FE9 Configuration rd only 0x0001FFA8 0x00007FEA Multicast MAC ID low 0x0001FFAC 0x00007FEB Multicast MAC ID high 0x0001FFB0 0x00007FEC Multicast MAC IP 0x0001FFB4 0x00007FED reserved 0x0001FFB8 0x00007FEE reserved 0x0001FFBC 0x00007FEF reserved © 2010 Ingenieurbüro Für Ic-Technologie Page 48
Address map 3 Advanced Features ON byte address dword address register name 0x0001FFC0 0x00007FF0 DMA Control 0x0001FFC4 0x00007FF1 Receive Destination (avalon) 0x0001FFC8 0x00007FF2 Receive Source GMACII 0x0001FFCC 0x00007FF3 Receive Length 0x0001FFD0 0x00007FF4 Receive Checksum 0x0001FFD4 0x00007FF5 Transmit Source (avalon) 0x0001FFD8 0x00007FF6 Transmit Destination GMACII 0x0001FFDC 0x00007FF7 Transmit Length 0x0001FFE0 0x00007FF8 Transmit Checksum 0x0001FFE4 0x00007FF9 Ti
Define macros 1 ifi_gmacii_regs.
Define macros 2 ifi_gmacii_regs.
Define macros 3 ifi_gmacii_regs.
Define macros 4 ifi_gmacii_regs.
Define macros 5 ifi_gmacii_regs.
Define macros 6 ifi_gmacii_regs.
Define macros 7 ifi_gmacii_regs.
Define macros 8 ifi_gmacii_regs.
Version Byte 3 Bit 31 30 29 28 27 26 25 24 read Month 7 Month 6 Month 5 Month 4 Month 3 Month 2 Month 1 Month 0 Bit 23 22 21 20 19 18 17 16 read Year 7 Year 6 Year 5 Year 4 Year 3 Year 2 Year 1 Year 0 Bit 15 14 13 12 11 10 9 8 read Quartus 7 Quartus 6 Quartus 5 Quartus 4 Quartus 3 Quartus 2 Quartus 1 Quartus 0 Bit 7 6 5 4 3 2 1 0 read Core rev 7 Core rev 6 Core rev 5 Core rev 4 Core rev 3 Core rev 2 Core rev 1 Core rev 0 write Byte 2
Details DMA the GMACII includes an internal DMA controller with special features: alignment aware and byte exact the GMACII-DMA is able to copy an exact number of bytes from the source (byteaddress) to the destination (byteaddress), with this feature we get the high copy-performance of up to 4 Bytes/clk_cycle even when the databytes need to be shifted 1,2 or 3 bytes (limitation: we read some bytes more than we need) checksum logic all written bytes are going into the checksum-adder, so after each copy
Details transmitter padding starting with revision 1.
Filter Details MAC-ID Filtering the MAC-ID, the MAC-IP and IP-Header is implemented to reduce the overhead in comparing the received frames for the cpu in embedded systems MAC-ID filter: Each device has to have it's own MAC-ID, which has to be loaded into the GMACII-core by software (MAC ID low - the last 32 bit and MAC ID high - the first 16 bit). The MAC-ID filter decodes the first 6 bytes of each received frame (called Destination Address) and compares to that loaded value.
Filter Details MAC-IP MAC-IP filter: Each device has to have it's own MAC-IP, which has to be loaded into the GMACII-core by software this IP can be fixed, or received from a DHCP-server depending on the systems structure. The MAC-IP filter decodes the Destination IP Address and compares to the loaded value. If all 32 bit match, the received frame is accepted. Additionally a Destination Address of "FF FF FF FF" is accepted as broadcast.
Filter Details frame types and length We have a filter to detect the type of the frame − − ARP IP which is divided in 1. 2. 3. 4. ICMP IGMP UDP/IP TCP/IP internet control message protocol internet group management protocol user datagram protocol Transmission control protocol For IP we can test if the announced total length is matching the real frame length with revisions until 1.
Summary for older GMACII revisions ARP request filter: Only valid ARP-requests are accepted (length and type) ICMP request filter: Only valid ICMP-requests (ping request) are accepted (length and type, echo request) IP filter: Only UDP/IP frames and TCP/IP frames are accepted, other types are discarded (length and type) LEN filter: To minimize the test-overhead for the cpu, the length of ARP-requests (fix), ICMP-requests and IP-frames is validated, this can not be switched off.
Reference-software for NIOS II and IDE project template in the IDE − IFI_hello_GMACII Files − ifi_hello_gmacii.h − ifi_hello_gmacii.c Settings Example application − ifi_phy_manager.c − ifi_tftp_server.c Configuration and communication with the PHY Manager TFTP Server routine − ifi_tftp_client.c − ifi_udp_burst.c − ifi_arp_reply.c TFTP client routine UDP burst routine ARP reply routine − ifi_arp_request.c − ifi_ping_reply.
Open ifi_hello_gmacii.
Burst Destination MAC Burst Destination IP © 2010 Ingenieurbüro Für Ic-Technologie Page 67
Second set of MAC and IP address − Change the comments to use this © 2010 Ingenieurbüro Für Ic-Technologie Page 68
Reference Software Flow UDP Burst 0 USE YVALID FOR UDP BURST Timer controlled © 2010 Ingenieurbüro Für Ic-Technologie Page 69 1 Hardware Trigger controlled
Timer controlled UDP BURST = 1 USE YVALID FOR UDP BURST = 0 OPEN_UDP_TX make header initialize No Yes Loopcount > 0 WRITE_UDP_TX transmit IFI_UDP_DATA_SIZE bytes in frames with IFI_UDP_MTU UDP data from ON CHIP DPRAM 4k Done No Looptime over Yes © 2010 Ingenieurbüro Für Ic-Technologie Page 70
Hardware Trigger controlled UDP BURST = 1 USE YVALID FOR UDP BURST = 1 No YVALID changed Yes OPEN_UDP_TX No Yes Loopcount > 0 make header initialize Done WRITE_UDP_TX transmit IFI_UDP_DATA_SIZE bytes in frames with IFI_UDP_MTU UDP data from IFI_DPRAM_REFDESIGN © 2010 Ingenieurbüro Für Ic-Technologie Page 71
Ethernet Background Protocol Stack Fundamentals UDP TCP what is theoretical possible © 2004 Altera Corporation
Protocol Stack Fundamentals The layered model Protocol stacks are made up of layers OSI 7 layer model of a network is a common representation Application Presentation LLC LOGICAL LINK CONTROL MAC MEDIA ACCESS CONTROL Session Transport Network Data Link PLS PHYSICAL SIGNALING AUI ATTACHMENT UNIT INTERFACE PMA PHYSICAL MEDIUM ATTACHMENT Physical MDI MEDIUM DEPENDENT INTERFACE MEDIUM © 2010 Ingenieurbüro Für Ic-Technologie Page 73
Protocol Stack Fundamentals The MAC Frame 7 Byte Clocksynchronisation Start-Frame-Delimiter LLC LOGICAL LINK CONTROL MAC MEDIA ACCESS CONTROL PLS PHYSICAL SIGNALING Destination Address 6 Byte MAC ID Source Address 6 Byte MAC ID 2 Byte Length/Typ AUI ATTACHMENT UNIT INTERFACE PMA PHYSICAL MEDIUM ATTACHMENT MDI MEDIUM DEPENDENT INTERFACE MEDIUM © 2010 Ingenieurbüro Für Ic-Technologie Page 74 MAC Data 4 Byte CRC
Protocol Stack Fundamentals Example: IP for TCP/IP or UDP/IP − Internet Protocol - IP 2 Byte Version / Type 2 Byte Total Length 7 Byte Clocksynchronisation 2 Byte Identification Start-Frame-Delimiter 2 Byte Flags and Fragment Offset Destination Address 6 Byte MAC ID 2 Byte Time to Live and Protocol Source Address 6 Byte MAC ID 2 Byte IP Header Checksum 2 Byte Length/Typ 4 Byte IP Source Address MAC Data 4 Byte CRC 4 Byte IP Destination Address X Byte Data(IP) © 2010 Ingenieurbüro Für Ic-Technol
Protocol Stack Fundamentals Example: UDP for UDP/IP − User Datagramm Protocol - UDP 7 Byte Clocksynchronisation Start-Frame-Delimiter Destination Address 6 Byte MAC ID 2 Byte Source Port Source Address 6 Byte MAC ID 2 Byte Destination Port 2 Byte Length / Typ 2 Byte Length IP Header 2 Byte UDP Checksum IP Data 4 Byte CRC X Byte Data You have to process all of your data to calculate the checksum © 2010 Ingenieurbüro Für Ic-Technologie Page 76
UDP – User Datagram Protocol Simplest IP protocol for applications Limited reliability − − − No guarantee of delivery No Handshake No Timeout Ports − Each application uses different port(s) Checksums the data − Optional © 2010 Ingenieurbüro Für Ic-Technologie Page 77
Protocol Stack Fundamentals Example: TFTP for UDP/IP − Trivial File Transfer Protocol - TFTP 7 Byte Clocksynchronisation Start-Frame-Delimiter Destination Address 6 Byte MAC ID Source Address 6 Byte MAC ID 2 Byte Length / Typ IP Header 2 Byte Opcode UDP Header 2 Byte Block Number UDP Data 4 Byte CRC © 2010 Ingenieurbüro Für Ic-Technologie Page 78 X Byte Data
Protocol Stack Fundamentals Example: TCP for TCP/IP − Transmission Control Protocol - TCP 2 Byte Source Port 2 Byte Destination Port 7 Byte Clocksynchronisation Start-Frame-Delimiter 4 Byte Sequence Number Destination Address 6 Byte MAC ID 4 Byte Acknowledgement Number Source Address 6 Byte MAC ID 2 Byte Control 2 Byte Length / Typ 2 Byte Window IP Header 2 Byte TCP Checksum IP Data 4 Byte CRC X Byte Data You have to process all of your data to calculate the checksum © 2010 Ingenieurbüro Für Ic
TCP – Transmission Control Protocol Reliable − − − Guaranteed delivery – using sequence numbers and acknowledgements Protocol has to exchange sequence numbers at startup Checksums the data Flow control − − Stacks advertise their available buffer space Algorithms to minimise congestion Also provides ports © 2010 Ingenieurbüro Für Ic-Technologie Page 80
Other protocols DHCP - Dynamic Host Configuration Protocol − Automatically assign an IP Address ARP – Address Resolution Protocol − Get the MAC address for a known IP Address ICMP – Internet Control Message Protocol − Echo Request / Echo Reply − Used by Ping IGMP – Internet Group Management Protocol − Used to manage multicasting © 2010 Ingenieurbüro Für Ic-Technologie Page 81
What’s theoretical possible 1000 Million Bit/s on the line − 119,2 MByte/s gross amount (1 MByte = 1048576 Byte) − without the minimum Interframe Gap (12 byte) For a 1518 Byte Frame the rate drops to 118 MByte/s − without the Preamble, Address, Typ, CRC (another 26 byte) For a 1518 Byte Frame the rate drops to 116 MByte/s − without the IP Header (20 byte) For a 1518 Byte Frame the rate drops to 115 MByte/s − without the UDP Header (8 byte) For a 1518 Byte Frame (1472 byte load) − the
What’s theoretical possible On PC-Side − The networkcard Datapath may be limited by PCI Bus (32 Bit 33 MHz max 132 MByte/s) Interruptfilter Latency − Depending from your OS switch it off or play with the settings Checksum Offloading … Jumboframe support − Harddrive performance Try a ramdisc to see the possible datarates − The OS may run into performance issues when the taskswitching rate gets to high © 2010 Ingenieurbüro Für Ic-Technologie Page 83
Revision History Revisio n Date Description Versioncode 1.0 Aug 2005 Initial release 0x07055010 1.2 Nov 2005 Compatible to 5.0 1.3 Feb 2006 1.4 Feb 2006 Lost data when DMA fifo runs empty Issue with arp_request fixed 0x02065114 1.5 Apr 2006 Issue when writing to slow memory fixed 0x03065115 1.6 Aug 2006 Changes in frequeny detection (now we use RX_CLK) Compatible to 6.0 0x08066016 1.7 Jan 2007 Enhancements like jumboframes, filters … Compatible to 6.1 0x01076117 9.
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2. License Restrictions: YOU MAY NOT USE THE IFI IP-MODULE EXCEPT AS EXPRESSLY PROVIDED FOR IN THIS AGREEMENT OR SUBLICENSE OR TRANSFER THE IFI IPMODULE OR RIGHTS WITH RESPECT THERETO.
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IFI Products and Services Dedicated to Altera since 1985 IPs − − − − − GMACII CAN2.0B USB MediaLB IEEE 1588 Training Classes − − − − IFI – QUARTUS IFI – ALTERA Expert IFI – VHDL IFI – Nios®II Design services for all ALTERA devices Consulting INGENIEURBÜRO FÜR IC-TECHNOLOGIE © 2010 Ingenieurbüro Für Ic-Technologie Page 89 Peter Riekert & Franz Sprenger Kleiner Weg 3 97877 Wertheim Germany Tel.: (+49)9342 / 9608-0 Fax: (+49)9342 / 5381 eMail: ifi @ ifi-pld.de http://www.ifi-pld.
