Specifications

Altera Corporation 1–33
October 2007
Nios II Hardware Development Tutorial Creating the Example Design
You must compile the hardware design to create an SRAM Object File that
you can download to the board. After the compilation completes, you
must analyze the timing performance of the FPGA design to verify that
the design will work in hardware.
Perform the following steps:
1. On the Processing menu, click Start Compilation.
2. The Quartus II Status utility window displays progress. The
compilation process can take several minutes. When compilation
completes, a dialog box displays the message "Full compilation was
successful."
3. Click OK. The Quartus II software displays the Compilation Report
window.
4. Expand the Timing Analyzer category of the Compilation Report
window.
5. Click Summary.
6. Check the frequency listed in the Actual Time cell associated with
PLD_CLOCKINPUT[1]. This is the maximum frequency (F
MAX
)
that this FPGA design is capable of running.
1 If the Actual Time frequency for PLD_CLOCKINPUT[1] is less
than the oscillator frequency on the board, this design will not
operate in hardware. You must make Quartus II timing
assignments to optimize the clock, or reduce the oscillator
frequency driving the FPGA.
Congratulations! You have finished integrating the Nios II system into
the Quartus II project. You are ready to download the SRAM Object File
to the target board.
f For further details on meeting timing requirements in the Quartus II
software, see the Quartus II Handbook Volume 1: Design and Synthesis.
Download Hardware Design to Target FPGA
In this section you download the SRAM Object File to the target board.
Perform the following steps:
1. Connect the board to the host computer with the download cable,
and apply power to the board.