Specifications
1–32 Altera Corporation
October 2007
Creating the Example Design Nios II Hardware Development Tutorial
Figure 1–17. Assigning Pins with the Quartus II Pin Planner
5. If you connected the LED pins in the Board Design File schematic,
repeat steps 2 to 4 with LEDG[7..0] to assign appropriate pin
locations for each of the LED outputs pins: LEDG[0], LEDG[1],
LEDG[2], LEDG[3], LEDG[4], LEDG[5], LEDG[6], LEDG[7].
6. On the File menu, click Save to save the assignments.
7. Close the Pin Planner.
c Depending on the board, you might have to make more
assignments for the project to function correctly. You can
damage the board if you fail to account for the board design.
Consult with the maker of the board to ensure that the following
conditions will not damage the board:
■ After power-up all unused I/O pins on the FPGA enter a high-
impedance state.
■ The IO banks are configured for the 3.3V LVTTL I/O standard. The
board must supply 3.3V to the FPGA's VCCIO pins.
■ The LEDG[7..0] outputs drive 3.3V.
f For further details on making assignments in the Quartus II software, see
the Quartus II Handbook Volume 2: Design Implementation and Optimization.
Compile the Quartus II Project and Verify Timing
At this point you are ready to compile the Quartus II project and verify
that the resulting design meets timing requirements.