Specifications

1–28 Altera Corporation
October 2007
Creating the Example Design Nios II Hardware Development Tutorial
f For further details on generating systems with SOPC Builder, see the
Quartus II Handbook Volume 4: SOPC Builder. For details on hardware
simulation for Nios II systems, see AN351: Simulating Nios II Embedded
Processor Designs.
Integrate the SOPC Builder System into the Quartus II Project
In this section you perform the following steps to complete the hardware
design:
■ Instantiate the SOPC Builder system module in the Quartus II
project.
■ Assign FPGA pins.
■ Compile the Quartus II project.
■ Ver if y t im in g.
1 You can skip ahead to “Develop Software Using the Nios II IDE”
on page 1–34 if you do not have a target board. Alternatively,
you can read this section to familiarize yourself with more of the
hardware design flow. However, the steps in this section do not
affect the outcome of the tutorial if you do not have a target
board.
f For further information on using the Quartus II software, see the Quartus
II Tutorial in the Quartus II help system, and both Introduction to the
Quartus II Software and the Quartus II Handbook, available at
www.altera.com/literature/lit-qts.jsp.
Instantiate the SOPC Builder System Module in the Quartus II Project
SOPC Builder outputs a design entity called the system module. The
tutorial example design uses the Block Diagram File method of design
entry, so you instantiate a system module symbol first_nios2_system into
the Block Diagram File.
1 How you instantiate the system module depends on the design
entry method of the overall Quartus II project. For example, if
you were using Verilog HDL for design entry, you would
instantiate the Verilog module first_nios2_system defined in
the file first_nios2_system.v.
To instantiate the system module in the Block Diagram File, perform the
following steps:
1. Double click in the empty space between the input and output pins.
The Symbol dialog box appears.