Specifications

Altera Corporation 1–19
October 2007
Nios II Hardware Development Tutorial Creating the Example Design
4. Click Caches and Memory Interfaces. The Caches and Memory
Interfaces page appears.
5. Specify the following settings (see Figure 1–7):
● Instruction Cache: 2 Kbytes
● Enable Bursts: Off
● Include tightly coupled instruction master port(s): Off
Figure 1–7. Nios II MegaWizard – Caches and Memory Interfaces page
6. Do not change any settings on the Advanced Features, JTAG
Debug Module, or Custom Instructions pages.
7. Click Finish. You return to the SOPC Builder System Contents tab,
and an instance of the Nios II core named cpu now appears in the
table of available components.
f For further details on configuring the Nios II core, see the Instantiating
the Nios II Processor in SOPC Builder chapter of the Nios II Processor
Reference Handbook.