Specifications

Altera Corporation 1–15
October 2007
Nios II Hardware Development Tutorial Creating the Example Design
Define the System in SOPC Builder
You use SOPC Builder to define the hardware characteristics of the Nios II
system, such as which Nios II core to use, and what components to
include in the system. SOPC Builder does not define software behavior,
such as where in memory to store instructions or where to send the
stderr character stream.
In this section, you perform the following steps:
1. Specify target FPGA and clock settings.
2. Add the Nios II core, on-chip memory, and other components.
3. Specify base addresses and interrupt request (IRQ) priorities.
4. Generate the SOPC Builder system.
The SOPC Builder design process does not need to be linear. The design
steps in this tutorial are presented in the most straightforward order for a
new user to understand. However, you can perform SOPC Builder design
steps in a different order.
Specify Target FPGA and Clock Settings
The Ta rg et and Clock Settings sections of the System Contents tab
specify the SOPC Builder system's relationship to other devices in the
system. Perform the following steps:
1. Select the Device Family that matches the Altera FPGA you are
targeting.
2. Double-click the clock frequency in the MHz column for clk. Type
the clock frequency as shown in Table 1–1, and press Enter. clk is
the default clock input name for the SOPC Builder system. The
frequency you specify for clk must match the oscillator that drives
the FPGA.
Table 1–1. Clock Frequency for Target Boards
Target Board Frequency
Nios Development Board (all versions),
or no board
50
Custom board Same as oscillator on board