Specifications

1–12 Altera Corporation
October 2007
Creating the Example Design Nios II Hardware Development Tutorial
The remainder of this tutorial refers to this directory as the <Design
Files Directory>.
Analyze System Requirements
This section describes the system requirements for the tutorial example
design. The goals for the design are the following:
■ Demonstrate a simple Nios II processor system that you can use for
control applications.
■ Build a practical, real-world system, while providing an educational
experience.
■ Demonstrate the most common and effective techniques to build
practical, custom Nios II systems.
■ Build a Nios II system that works on any board with an Altera FPGA.
The entire system must use only on-chip resources, and not rely on
the target board.
■ The design should conserve on-chip logic and memory resources so
it can fit in a wide range of target FPGAs.
These goals lead to the following design decisions:
■ The Nios II system uses only the following inputs and outputs:
● One clock input, which can be any constant frequency.
● Eight optional outputs to control LEDs on the target board.
■ The design uses the following components:
● Nios II/s core with 2 Kbytes of instruction cache
● 20 Kbytes of on-chip memory
● Timer
● JTAG UART
● Eight output-only parallel I/O (PIO) pins
● System ID component
f For complete details on these and other components, see the Quartus II
Handbook Volume 5: Embedded Peripherals.
Start the Quartus II Software and Open the Tutorial Example
Design Project
To start, you open the Quartus II project for the tutorial example design.
This Quartus II project serves as an easy starting point for the Nios II
development flow. The Quartus II project contains all settings and design
files required to create the SRAM Object File.
To open the Quartus II project, perform the following steps:
1. Start the Quartus II software.