Specifications
Altera Corporation 1–9
October 2007
Nios II Hardware Development Tutorial Nios II System Development Flow
■ system.h file – system.h defines symbols for referencing the
hardware in the system. The IDE automatically creates this file when
you create a new project.
■ Executable and Linkable Format File (.elf) – An Executable and
Linkable Format File is the result of compiling a C/C++ application
project, which you can download directly to the Nios II processor.
■ Memory initialization files (.hex) – Some on-chip memories can
power up with predefined memory contents. The IDE generates
initialization files for on-chip memories that support initialization of
contents.
■ Flash programming data – The IDE includes a flash programmer,
which allows you to write your program to flash memory. The flash
programmer adds appropriate boot code to allow your program to
boot from flash memory. You can also use the flash programmer to
write arbitrary data to flash memory.
This tutorial focuses only on downloading the Executable and Linkable
Format File directly to the Nios II system.
f For complete details on developing software for the Nios II processor,
see the Nios II Software Developer's Handbook and the Nios II IDE help
system.
Running and Debugging Software on the Target Board
The Nios II IDE provides complete facilities for downloading software to
a target board, and running or debugging the program on hardware. The
IDE debugger allows you to start and stop the processor, step through
code, set breakpoints, and analyze variables as the program executes.
f For details on running and debugging Nios II programs, see the Software
Development Tutorial available from the Nios II IDE help system.
Varying the Development Flow
The development flow is not strictly linear. This section describes
common variations.
Refining the Software and Hardware
After running software on the target board, you might discover that the
Nios II system requires higher performance. In this case, you can return
to software design steps to make improvements to the software
algorithm. Alternatively, you can return to hardware design steps to add
acceleration logic. If the system performs multiple mutually exclusive