Specifications

1–6 Altera Corporation
October 2007
Nios II System Development Flow Nios II Hardware Development Tutorial
The Nios II development flow consists of three types of development:
hardware design steps, software design steps, and system design steps,
involving both hardware and software. For simpler Nios II systems, one
person might perform all steps. For more complex systems, separate
hardware and software designers might be responsible for different steps.
System design steps involve both the hardware and software, and might
require input from both sides. In the case of separate hardware and
software teams, it is important to know exactly what files and
information must be passed between teams at the points of intersection in
the design flow.
The design steps in this tutorial focus on hardware development, and
provide only a simple introduction to software development. For further
details on the software development process, Altera recommends that
you read the Software Development Tutorial available from the Nios II IDE
help system after you complete this tutorial.
f The Software Development Tutorial and complete IDE reference are
included in the Nios II IDE help system. To open the Nios II IDE help
system, click Help Contents on the Help menu. To see the tutorials, click
Nios II IDE Help in the Contents pane, and then click Tutorials.
Analyzing System Requirements
The development flow begins with predesign activity which includes an
analysis of the application requirements, such as:
■ What computational performance does the application require?
■ How much bandwidth or throughput does the application require?
■ What types of interfaces does the application require?
■ Does the application require multithreaded software?
Based on the answers to these questions, you can determine the concrete
system requirements, such as:
■ Which Nios II processor core to use: smaller or faster?
■ What components does the design require? How many of each kind?
■ Which real-time operating system (RTOS) to use, if any?
■ Where can hardware acceleration logic dramatically improve system
performance? For example:
● Could adding a DMA component eliminate wasted processor
cycles copying data?
● Could a custom instruction replace the critical loop of a DSP
algorithm?
● Could the Nios II C-to-Hardware (C2H) Acceleration Compiler
improve performance?