Specifications

Altera Corporation 1–5
October 2007
Nios II Hardware Development Tutorial Nios II System Development Flow
Nios II System
Development
Flow
This section discusses the complete design flow for creating a Nios II
system and prototyping it on a target board. Figure 1–2 shows the Nios II
system development flow.
Figure 1–2. Nios II System Development Flow
Altera
Hardware
Abstraction
Layer
&
Peripheral
Drivers
Assign Pin
Locations,
Timing
Requirements
and Other
Design
Constraints
Run/Debug Software
on Target Board
Download
Software
Executable
to Nios II
System on
Target Board
Define & Generate
System in SOPC Builder
Download FPGA
Design toTarget
Board
Compile Hardware
Design for Target
Board
Analyze System
Requirements
Refine Software
and Hardware
User C/C++
Application
Code and
Custom
Libraries
Custom
Instruction
&
Custom
Peripheral
Logic
Custom
Hardware
Modules
Nios II
Cores
&
Standard
Peripherals
Develop
Software
with the
Nios II IDE
Run/Debug
Software Using
ISS in Nios II
IDE
Integrate SOPC
Builder System
into Quartus II
Project