Specifications

1–2 Altera Corporation
October 2007
Introduction Nios II Hardware Development Tutorial
Figure 1–1 is a block diagram showing the relationship between the host
computer, the target board, the FPGA, and the Nios II system.
Figure 1–1. Tutorial Example Design
As shown in Figure 1–1, other logic can exist within the FPGA alongside
the Nios II system. In fact, most FPGA designs with a Nios II system also
include other logic. A Nios II system can interact with other on-chip logic,
depending on the needs of the overall system. For the sake of simplicity,
the example design in this tutorial does not include other logic in the
FPGA.
Software and Hardware Requirements
This tutorial requires you to have the following software:
■ Altera Quartus II software version 7.1 or later – The software must be
installed on a Windows or Linux computer that meets the Quartus II
minimum requirements.
■ Nios II Embedded Design Suite version 7.1 or later
Nios II System
Character
I/O
Instr
Data
Debug
Control
8
Other
Logic
Altera FPGA
Target Board
LED5
LED0
LED1
LED2
LED3
LED4
LED6
LED7
VCC
Clock
Oscillator
System Interconnect Fabric
Timer
PIO
System
ID
On-Chip
RAM
Nios II/s
Core
JTAG
UART
JTAG Controller
10-pin
JTAG
Header