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Contents About this Tutorial ................................................................................. v How to Contact Altera ............................................................................................................................ vi Typographic Conventions ...................................................................................................................... vi Nios II Hardware Development ...................................................................
Contents Nios II Hardware Development Tutorial Create a New Nios II C/C++ Application Project ............................................................... Compile the Project ................................................................................................................... Run the Program ............................................................................................................................ Run the Program on Target Hardware ........................................
About this Tutorial This tutorial introduces you to the Altera® Nios®II-based system. It shows you how to use the Quartus®II software to create and process your own Nios II system design that interfaces with components on Nios development boards. Table 1–1 shows the tutorial revision history. f Refer to the Nios II Embedded Design Suite Release Notes and Nios II Embedded Design Suite Errata for the latest features, enhancements, and known issues in the current release. Table 1–1.
How to Contact Altera Nios II Hardware Development Tutorial How to Contact Altera For the most up-to-date information about Altera® products, refer to the following table. Contact (1) Contact Method Address Technical support Website www.altera.com/support Technical training Website www.altera.com/training Email custrain@altera.com Product literature Website www.altera.com/literature Altera literature services Email literature@altera.
Nios II Hardware Development Tutorial Visual Cue Courier type Typographic Conventions Meaning Signal and port names are shown in lowercase Courier type. Examples: data1, tdi, input. Active-low signals are denoted by suffix n, e.g., resetn. Anything that must be typed exactly as it appears is shown in Courier type. For example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual file, such as a Report File, references to parts of files (e.g.
Typographic Conventions viii Nios II Hardware Development Tutorial Altera Corporation
Nios II Hardware Development Introduction This tutorial introduces you to the system development flow for the Nios II processor. This tutorial is a good starting point if you are new to the Nios II processor or the general concept of building embedded systems in FPGAs. In this tutorial you build a Nios II hardware system and create a software program to run on the Nios II system.
Introduction Nios II Hardware Development Tutorial Figure 1–1 is a block diagram showing the relationship between the host computer, the target board, the FPGA, and the Nios II system. Figure 1–1.
Nios II Hardware Development Tutorial ■ Introduction Design files for the example design – A hyperlink to the design files appears next to this document on the Nios II literature page. Visit www.altera.com/literature/lit-nio2.jsp. You can build the example design in this tutorial whether you own a development board or not. This tutorial allows you to choose from the following target board options: ■ ■ f For information on Nios II development kits, visit www.altera.com/ devkits.
Introduction Nios II Hardware Development Tutorial when connecting to the Nios II processor. Revised cables have a clearly marked revision label; earlier cables do not. OpenCore Plus Evaluation You can perform this tutorial, even on hardware, without a license.
Nios II Hardware Development Tutorial Nios II System Development Flow Nios II System Development Flow This section discusses the complete design flow for creating a Nios II system and prototyping it on a target board. Figure 1–2 shows the Nios II system development flow. Figure 1–2.
Nios II System Development Flow Nios II Hardware Development Tutorial The Nios II development flow consists of three types of development: hardware design steps, software design steps, and system design steps, involving both hardware and software. For simpler Nios II systems, one person might perform all steps. For more complex systems, separate hardware and software designers might be responsible for different steps.
Nios II Hardware Development Tutorial Nios II System Development Flow Answers to these questions involve both the hardware and software teams. Defining and Generating the System in SOPC Builder After analyzing the system hardware requirements, you use the SOPC Builder tool which is included in the Altera Quartus II software. Using SOPC Builder you specify the Nios II processor core(s), memory, and other components your system requires.
Nios II System Development Flow Nios II Hardware Development Tutorial intellectual property (IP) design modules available from Altera or third party IP providers. This tutorial does not cover adding other logic outside the Nios II system. Using the Quartus II software, you also assign pin locations for I/O signals, specify timing requirements, and apply other design constraints. Finally, you compile the Quartus II project to produce an SRAM Object File to configure the FPGA.
Nios II Hardware Development Tutorial ■ ■ ■ ■ Nios II System Development Flow system.h file – system.h defines symbols for referencing the hardware in the system. The IDE automatically creates this file when you create a new project. Executable and Linkable Format File (.elf) – An Executable and Linkable Format File is the result of compiling a C/C++ application project, which you can download directly to the Nios II processor. Memory initialization files (.
Creating the Example Design Nios II Hardware Development Tutorial tasks, you might even decide to use two (or more) Nios II processors that divide the workload and improve the performance of each individual processor. Iteratively Creating a Nios II System A common technique for building a complex Nios II system is to start with a simpler SOPC Builder system, and iteratively add to it. At each iteration you can verify that the system performs as expected.
Nios II Hardware Development Tutorial Creating the Example Design 2. “Analyze System Requirements” on page 1–12. 3. “Start the Quartus II Software and Open the Tutorial Example Design Project” on page 1–12. 4. “Create a New SOPC Builder System” on page 1–14. 5. “Define the System in SOPC Builder” on page 1–15. 6. “Integrate the SOPC Builder System into the Quartus II Project” on page 1–28. 7. “Download Hardware Design to Target FPGA” on page 1–33. 8.
Creating the Example Design Nios II Hardware Development Tutorial The remainder of this tutorial refers to this directory as the . Analyze System Requirements This section describes the system requirements for the tutorial example design. The goals for the design are the following: ■ ■ ■ ■ ■ Demonstrate a simple Nios II processor system that you can use for control applications. Build a practical, real-world system, while providing an educational experience.
Nios II Hardware Development Tutorial Creating the Example Design On Windows computers, click Start, point to Programs, Altera, Quartus II , and then click Quartus II . On Linux computers, type quartus at a shell command-prompt, assuming the Quartus II program directory is in the search path. 2. On the File menu, click Open Project. Be careful not to mistake Open for Open Project. The Open Project dialog box appears. 3. Browse to . 4.
Creating the Example Design Nios II Hardware Development Tutorial Create a New SOPC Builder System You use SOPC Builder to generate the Nios II processor system, adding the desired components, and configuring how they connect together. Perform the following steps to create a new SOPC Builder system: 1. On the Tools menu in the Quartus II software, click SOPC Builder. SOPC Builder starts and displays the Create New System dialog box. 2. Type first_nios2_system as the System Name. 3.
Nios II Hardware Development Tutorial Creating the Example Design Define the System in SOPC Builder You use SOPC Builder to define the hardware characteristics of the Nios II system, such as which Nios II core to use, and what components to include in the system. SOPC Builder does not define software behavior, such as where in memory to store instructions or where to send the stderr character stream. In this section, you perform the following steps: 1. Specify target FPGA and clock settings. 2.
Creating the Example Design Nios II Hardware Development Tutorial Next, you begin to add hardware components to the SOPC Builder system. As you add each component, you configure it appropriately to match the design specifications. Add the On-Chip Memory Processor systems require at least one memory for data and instructions. This example design uses one 20 Kbyte on-chip memory for both data and instructions. To add the memory, perform the following steps: 1–16 1.
Nios II Hardware Development Tutorial Creating the Example Design Figure 1–5. On-Chip Memory MegaWizard 6. f Click Finish. You return to the SOPC Builder System Contents tab, and an instance of the on-chip memory named onchip_mem now appears in the table of available components. For further details on on-chip memory, you can click Documentation in the On-Chip Memory (RAM or ROM) MegaWizard interface. 1 This documentation feature is available in the MegaWizard interface for each component.
Creating the Example Design Nios II Hardware Development Tutorial provides a balanced trade-off between performance and resource utilization. In reality, the Nios II/s core is more powerful than necessary for most simple control applications. Perform the following steps to add a Nios II/s core to the system: 1. In the list of available components, select Nios II Processor. 2. Click Add. The Nios II Processor MegaWizard interface appears, displaying the Nios II Core page. 3.
Nios II Hardware Development Tutorial Creating the Example Design 4. Click Caches and Memory Interfaces. The Caches and Memory Interfaces page appears. 5. Specify the following settings (see Figure 1–7): ● ● ● Instruction Cache: 2 Kbytes Enable Bursts: Off Include tightly coupled instruction master port(s): Off Figure 1–7. Nios II MegaWizard – Caches and Memory Interfaces page f Altera Corporation October 2007 6.
Creating the Example Design 1 Nios II Hardware Development Tutorial SOPC Builder automatically connects the instruction and data master ports on the Nios II core to the memory slave port (see Figure 1–8). When building a system, always verify that SOPC Builder's automatic connections are appropriate for your system requirements. Figure 1–8.
Nios II Hardware Development Tutorial Creating the Example Design Figure 1–9. JTAG UART MegaWizard 4. 1 f Click Finish. You return to the SOPC Builder System Contents tab, and an instance of the JTAG UART named jtag_uart now appears in the table of available components. SOPC Builder automatically connects the data master port on the Nios II core to the JTAG UART slave port.
Creating the Example Design Nios II Hardware Development Tutorial 1. In the list of available components, expand Peripherals, expand Microcontroller Peripherals, and then click Interval Timer. 2. Click Add. The Interval Timer MegaWizard interface appears. 3. In the Presets list, select Full-featured. 4. Do not change any of the other default settings (see Figure 1–10). Figure 1–10. Interval Timer MegaWizard 1–22 5. Click Finish.
Nios II Hardware Development Tutorial 1 f Creating the Example Design It is a good habit to give memorable names to hardware components. Nios II programs use these symbolic names to access the component hardware. Therefore, your choice of component names can make Nios II programs easier to read and understand. For further details on the timer, see the Timer Core chapter of the Quartus II Handbook Volume 5: Embedded Peripherals.
Creating the Example Design Nios II Hardware Development Tutorial Add the PIO PIO signals provide an easy method for Nios II processor systems to receive input stimuli and drive output signals. Complex control applications might use hundreds of PIO signals which the Nios II processor can monitor. This example design uses eight PIO signals to drive LEDs on the board. Perform the following steps to add the PIO. Perform these steps even if your target board doesn't have LEDs. 1.
Nios II Hardware Development Tutorial 4. Click Finish. You return to the SOPC Builder System Contents tab, and an instance of the PIO named pio now appears in the table of available components. 5. Right-click pio and click Rename. 6. Type led_pio and press Enter. 1 f Creating the Example Design Nios II software uses this name to access the component. You must name the PIO led_pio, or else tutorial programs written for this Nios II system will fail to work in later steps.
Creating the Example Design Nios II Hardware Development Tutorial responds to them. Because SOPC Builder does not deal with software behavior, it cannot make educated guesses about the best IRQ assignment. The Nios II HAL interprets low IRQ values as higher priority. The timer component must have the highest IRQ priority to maintain the accuracy of the system clock tick. To assign appropriate base addresses and IRQs, perform the following steps: 1.
Nios II Hardware Development Tutorial Creating the Example Design 1. Click the System Generation tab. 2. Turn off Simulation. Create simulator project files., which saves time because this tutorial does not cover the hardware simulation flow. 3. Click Generate. The system generation process begins. The generation process can take several minutes. When it completes, the System Generation tab displays a message "Info: System generation was successful." (see Figure 1–14). Figure 1–14.
Creating the Example Design f Nios II Hardware Development Tutorial For further details on generating systems with SOPC Builder, see the Quartus II Handbook Volume 4: SOPC Builder. For details on hardware simulation for Nios II systems, see AN351: Simulating Nios II Embedded Processor Designs.
Nios II Hardware Development Tutorial Creating the Example Design 2. Under Libraries:, expand Project. 3. Click first_nios2_system. The Symbol dialog box displays the first_nios2_system symbol. 4. Click OK. You return to the Block Diagram File schematic. The first_nios2_system symbol tracks with your mouse pointer. 5. Position the symbol so the inputs on the symbol align with the wires on the left-hand side of the Block Diagram File. 6. Click the left mouse button to drop the symbol in place. 7.
Creating the Example Design Nios II Hardware Development Tutorial Assign FPGA pins If you are targeting a custom board, you must assign a specific target device and then assign FPGA pin locations to match the pinouts of your board. 1 Skip ahead to section “Compile the Quartus II Project and Verify Timing” on page 1–32, if you are targeting a Nios development board. The provided Quartus II project files already contain appropriate assignments for Nios development boards.
Nios II Hardware Development Tutorial Creating the Example Design Figure 1–16 shows an example of the Settings dialog box assigning a Cyclone device. Figure 1–16. Assigning a Device in the Quartus II Settings Dialog Box To assign the FPGA pin locations, perform the following steps: Altera Corporation October 2007 1. On the Assignments menu, click Pins. The Quartus II Pin Planner appears.
Creating the Example Design Nios II Hardware Development Tutorial Figure 1–17. Assigning Pins with the Quartus II Pin Planner 5. If you connected the LED pins in the Board Design File schematic, repeat steps 2 to 4 with LEDG[7..0] to assign appropriate pin locations for each of the LED outputs pins: LEDG[0], LEDG[1], LEDG[2], LEDG[3], LEDG[4], LEDG[5], LEDG[6], LEDG[7]. 6. On the File menu, click Save to save the assignments. 7. Close the Pin Planner.
Nios II Hardware Development Tutorial Creating the Example Design You must compile the hardware design to create an SRAM Object File that you can download to the board. After the compilation completes, you must analyze the timing performance of the FPGA design to verify that the design will work in hardware. Perform the following steps: 1. On the Processing menu, click Start Compilation. 2. The Quartus II Status utility window displays progress. The compilation process can take several minutes.
Creating the Example Design Nios II Hardware Development Tutorial 2. On the Tools menu in the Quartus II software, click Programmer. The Programmer window appears and automatically displays the appropriate configuration file (nios2_quartus2_project.sof). 3. Click Hardware Setup in the top-left corner of the Programmer window to verify your download cable settings. The Hardware Setup dialog box appears. 4. Select the appropriate download cable in the Currently selected hardware list.
Nios II Hardware Development Tutorial ■ ■ Creating the Example Design Create a new Nios II C/C++ application project (see page 1–35). Compile the project (see page 1–36). To perform this section, you must have the SOPC Builder System File you created in “Define the System in SOPC Builder” on page 1–15. Create a New Nios II C/C++ Application Project In this section you create a new Nios II C/C++ Application Project. Perform the following steps: 1. Start the Nios II IDE.
Creating the Example Design Nios II Hardware Development Tutorial Figure 1–19. Nios II IDE New Project Wizard The Nios II IDE creates and displays these new projects in the Nios II C/ C++ Projects view on the left-hand side of the workbench: ■ ■ ■ count_binary_0 - Your C/C++ application project count_binary_0_syslib - A board support package that encapsulates the details of the Nios II system hardware altera.
Nios II Hardware Development Tutorial Creating the Example Design Perform the following steps: 1. Right-click count_binary_0 and click System Library Properties. The Properties dialog box for count_binary_0_syslib opens. 2. Click the System Library page. The System Library page contains all settings related to how the program interacts with the underlying hardware.
Creating the Example Design Nios II Hardware Development Tutorial Figure 1–20. System Library Properties 4. Click OK to close the Properties dialog box and return to the IDE workbench. 5. Right-click the count_binary_0 project in the Nios II C/C++ Projects view and click Build Project. The Build Project dialog box appears, and the IDE begins compiling the project. When compilation completes, a "Build completed" message appears in the Console view.
Nios II Hardware Development Tutorial Creating the Example Design Run the Program on Target Hardware In this section you download the program to target hardware and execute it. 1 If you do not have a target board, skip ahead to “Run the Program on the ISS” on page 1–40. To proceed, you must have completed the steps in “Download Hardware Design to Target FPGA” on page 1–33. To download the software executable to the target board, perform the following steps: 1.
Creating the Example Design Nios II Hardware Development Tutorial You can make edits to the count_binary.c program in the IDE and repeat these two steps to witness your changes executing on the target board. If you rerun the program, buffered characters from the previous run session might display in the Console view before the program begins executing. f For information on running and debugging programs on target hardware, see the Software Development Tutorial available from the Nios II IDE help system.
Nios II Hardware Development Tutorial f Taking the Next Step Taking the Next Step For information on running and debugging programs on the ISS, see the Software Development Tutorial available from the Nios II IDE help system. Congratulations! You have completed building a Nios II hardware system and running software on it.
Taking the Next Step 1–42 Nios II Hardware Development Tutorial Altera Corporation October 2007
