User guide

16 Altera Corporation
EPXA1 Development Kit Getting Started User Guide Getting Started
– External clock reference: 25 MHz
– Bypass PLL1: turn off
– Desired AHB1 frequency: 160 MHz
– AHB2 frequency: 80 MHz
– SDRAM Frequency: 133 MHz
1 The EPXA1 board uses a 25-MHz oscillator for the reference
clock. The AHB1 clock setting is for a –2 speed grade of the
EPXA1 device.
8. Specify the following settings and click Next:
– Registers: 7FFFC000 address, 16K size
– SRAM0: 20000000 address, 16K size
– SRAM1: 20004000 address, 16K size
– SDRAM0: 00000000 address, 64M size
– EBI0 (FLASH): 40000000 address, 4M size, 8 Wait cycles, Low CS
polarity, 16-bit Data Width, 1 Bus clock divide
– PLD0: 80000000 address, 16K size
1 When you enter the EBI0(FLASH) address, the remaining
EBI0(FLASH) settings appear. When you enter the SDRAM0
address, the remaining SDRAM0 settings appear. Choose
Micron MT48LC16M16A2 as the SDRAM device, and
ensure that the SDRAM port width is set to 16 bits .
9. Click Finish to create the software header files and the Verilog HDL
instantiation of the stripe.
Compile the
Hardware
Design
The example design has already been pre-built. To become familiar with
the process, or to modify it for your own designs, perform the following
steps to compile the hardware design:
1. Choose Settings (Assignments menu).
2. Under Category, expand Compiler Settings and choose Device.
3. Choose the following settings:
– Family: Excalibur ARM
–Target device: Specific device selected
– Available devices: EPXA1F484C1
4. Click Device & Pin Options.
5. Click the General tab and choose the following:
– Enable INIT_DONE output: turn on