Specifications

Altera Corporation 49
EPXA1 Development Board Hardware Reference Manual
Test Core Functionality
The EPXA1 board is supplied with a diagnostic software image directly
programmed into flash memory. When the embedded processor boots, it
configures the FPGA and runs the software using the test FPGA image.
The software is controlled using a serial terminal connected to the board
connector, P2, and the following PC communications port settings: baud
rate 38400, 8 data bits, no parity, one stop bit and no flow control.
 Ensure that the serial terminal program is configured to output
carriage return and line feeds—not all terminals default to these
settings.
The options on the software menu are as follows:
e—Run Ethernet internal loopback test
E—Run Ethernet external loopback test (requires loopback
connector)
h—Show this screen
i—Show interrupt usage
m—Run memory test
t—Toggle terminal output between UARTS
■ The Ethernet internal loopback test checks that the Ethernet chip is
working properly—the external loopback test is for manufacturing
test only
■ The toggle between the UARTS switches the output of the program
between P1 and P2. P2 is connected to the UART in the EPXA1
embedded stripe; P1 is connected to a UART which has been
programmed into the FPGA. After switching the port using the t
command, you can connect the serial terminal to the currently-
unused serial connector (i.e., if you were using P2, you will now use
P1), and type h↵ to invoke the help menu.
■ The memory test tests the integrity of the SDRAM on the board.
In addition, the LEDS and switches can be tested as follows:
■ Each of the eight switches on the switch block can turn the
corresponding LED on or off; for example, SW6_1 turns on the first
LED
■ When held down, SW5 toggles the 9th LED
■ When held down, SW4 toggles the 10th LED
■ When held down, SW3 inverts the current setting of all the LEDS
■ SW2 shifts all the LEDS right (as viewed) by one place