Specifications

44 Altera Corporation
EPXA1 Development Board Hardware Reference Manual
UART1 & UART2
Table 33 details the pins used for UARTs 1 and 2.
Fast I/O Pins
Table 34 details the EPXA1 fast I/O pins, which are used as expansion
header clock inputs.
Table 33. UARTs 1 & 2 I/O Pin-Outs
FPGA UART Embedded Stripe UART
EPXA1 I/O
Pin
Connector
Pin
Device
Signal
EPXA1
Device Pin
Connector
Pin
Device
Signal
K4 P1.4 DTR E6 P2.4 XA_DTR
J1 P1.3 TXD G5 P2.3 XA_TXD
K5 P1.2 RXD F2 P2.2 XA_RXD
L5 P1.6 DSR G4 P2.6 XA_DSR
K3 P1.7 RTS E2 P2.7 XA_RTS
L7 P1.9 RI F3 P2.9 XA_RI
L6 P1.1 DCD F6 P2.1 XA_DCD
L4 P1.8 CTS F1 P2.8 XA_CTS
P1.5 GND P2.5 GND
Table 34. EPXA1 Fast I/O Pins
EPXA1 Pin Name Board Signal Description EPXA1 Pin Expansion Header Card
Connector
FAST1 H5V_CLKOUT Dedicated fast I/O pin J2 J3.13
FAST4 H5V_CLKOUT Dedicated fast I/O pin W12 J10.13