Specifications

Altera Corporation 41
EPXA1 Development Board Hardware Reference Manual
Table 30 lists the SDRAM data and address bus pin-outs.
Table 30. SDR SDRAM Data Bank & Address Bus Pin-Outs
Signal Name EPXA1 Device
Pin
Board
Reference
Signal Name EPXA1 Device
Pin
Board
Reference
SD_DQ0 B20 U13.2 SD_DQ1 C20 U13.4
SD_DQ2 F18 U13.5 SD_DQ3 C21 U13.7
SD_DQ4 E20 U13.8 SD_DQ5 F19 U13.10
SD_DQ6 F20 U13.11 SD_DQ7 G18 U13.13
SD_DQ8 H19 U13.42 SD_DQ9 G20 U13.44
SD_DQ10 E22 U13.45 SD_DQ11 H18 U13.47
SD_DQ12 G21 U13.48 SD_DQ13 H20 U13.50
SD_DQ14 H17 U13.51 SD_DQ15 H22 U13.53
SD_A0 B17 U13.23 SD_A1 G16 U13.24
SD_A2 D16 U13.25 SD_A3 F16 U13.26
SD_A4 A19 U13.29 SD_A5 E16 U13.30
SD_A6 B18 U13.31 SD_A7 F17 U13.32
SD_A8 C17 U13.33 SD_A9 D17 U13.34
SD_A10 B19 U13.22 SD_A11 D18 U13.35
SD_A12 D19 U13.36 SD_A13 C19 U13.20
SD_A14 E18 U13.21