Specifications

40 Altera Corporation

EPXA1 Development Board Hardware Reference Manual

SDR SDRAM Interface

The EPXA1 development board contains one 16-bit SDR SDRAM device

connected to the EPXA1 SDRAM controller.

For further details about the SDRAM controller, refer to the Excalibur

Devices Hardware Reference Manual.

The SDRAM_DQM[1:0] lines are used as byte enables for both reading

from and writing to the SDRAM.

Table 29 shows the pin-outs for the SDR SDRAM control signals.

Note:

(1) These pins are tied together to provide a data-read strobe. See the Excalibur Devices Hardware Reference Manual.

DEV_OE U16 Device output enable. GPIO

nWS M21 Write strobe. GPIO

nRS P16 Read strobe. GPIO

nCS N20 Signal providing handshaking between devices. GPIO

CS P17 Chip select. GPIO

RDYnBSY K4 Ready/busy. GPIO

CLKUSR L7 Clock signal. GPIO

Table 28. EPXA1 Device Configuration Pins (Part 2 of 2)

Signal Name EPXA1 Device

Board

Reference

Description

Table 29. SDR SDRAM Control Signal Pin-Outs

Signal Name EPXA1 Device Pin Board Reference Description

SD_RAS_N C14 U13.18 Row address strobe

SD_CAS_N A17 U13.17 Column address strobe

SD_WE_N F14 U13.16 Write enable

SD_CS0_N G15 U13.19 Chip select

SD_CLKE E15 U13.37 Clock enable

SD_CLK C15 U13.38 SDRAM clock

SD_CLK_N(1) J16 Read data strobe output in SDR mode

SD_DQM[0] E21 U13.15 Data byte mask

SD_DQM[1] J20 U13.39 Data byte mask

SD_DQS[0](1) D22 Read data strobe input in SDR mode

SD_DQM_ECC B13 Not used