Specifications

Altera Corporation 39
EPXA1 Development Board Hardware Reference Manual
Configuration
The EPXA1 device pins listed in Table 28 on page 39 are used exclusively
for configuring the device. Refer to “Device Configuration” on page 28 for
more information about EPXA1 configuration.
Table 28. EPXA1 Device Configuration Pins (Part 1 of 2)
Signal Name EPXA1 Device
Pin
Board
Reference
Description
MSEL0 R5 Configuration mode select (tied to GND)
MSEL1 T3 Configuration mode select (tied to GND)
BOOT_FLASH J5 Tied high (mandatory boot from flash)
NSTATUS AB12 Pulled high
NCONFIG R4 Connected to SOFT_RESET line
DCLK R16 Pulled high
CONF_DONE V12 Pulled high
INIT_DONE K7 Initialization complete LED
nCE P19 Pulled low
nCEO H3 Not connected
DATA0 P18 Pulled low
DATA1 K3 Unused. Used as general-purpose I/O
DATA2 J1
DATA3 L5
DATA4 L4
DATA5 L6
DATA6 L22
DATA7 M18
TDI T20 J6.9 JTAG data input
TDO J4 J6.3 JTAG data output (to next device in the chain
TCK Y11 J6.1 JTAG clock
TMS U11 J6.5 JTAG mode select
TRST J6 JTAG reset (pulled high)
PROC_TDI G7 J8.5 JTAG data input
PROC_TDO G2 J8.13 JTAG data output (to next device in the chain)
PROC_TCK G3 J8.9 JTAG clock
PROC_TMS H6 J8.7 JTAG mode select
PROC_TRST G6 J8.3 JTAG reset (pulled high)
DEV_CLR_n R20 T15, T14 FPGA clear signal taken to test pad T15, placed next to
grounded test pad T14 near SW1; allows use of this signal, if
required