Specifications

38 Altera Corporation
EPXA1 Development Board Hardware Reference Manual
Development
Board Pin-Outs
The main component of the EPXA1 development board is the EPXA1F484
device. The pins on the EPXA1 device are assigned to functions on the
board. When generating IP cores for the EPXA1 device, the pins must be
used as defined to avoid damaging the device and any unused pins
should be tri-stated using the Quartus II software. The following sections
list the interfaces and dedicated pins on the board. Any pins not used for
a design should be left in a high-impedance state to avoid contention.
This section details the pins on the EPXA1 device which are assigned to
the following purposes:
■ Configuration
■ SDR SDRAM
■ EBI—for the Ethernet and flash memory devices
■ UARTs 1 and 2
■ Fast I/O pins
■ Expansion headers
■ Prototyping area
■ Test pads
Pin assignments are grouped into tables for control pins, address pins,
and data bus pins where appropriate. The tables also detail signals
passing across a connection. The remaining I/O pins on the EPXA1 device
are listed at the end of this section.
15 NSRST Warm reset I/O
16 GND Ground N/A
17 NC No connection N/A
18 GND Ground N/A
19 NC No connection N/A
20 GND Ground N/A
Table 27. Multi-ICE Connector Signals (Part 2 of 2)
Pin Signal Description Direction