Specifications

Altera Corporation 37
EPXA1 Development Board Hardware Reference Manual
Configuration/Debugging Interfaces
On the development board, there are interfaces for a MasterBlaster or
ByteBlasterMV cable, and a Multi-ICE connector. Table 26 lists the signals
on the MasterBlaster/ByteBlasterMV connector. Table 27 lists the signals
on the Multi-ICE connector. Table 28 on page 39 lists pin-out information
for the development board configuration and debugging interfaces.
Table 26. MasterBlaster/ByteBlasterMV Female Connector Signals
Pin JTAG Mode
Signal Description
1 TCK Clock signal
2 GND Signal ground
3 TDO Data from device
4 V
CC
Power supply
5 TMS JTAG state machine control
6 V
IO
Reference voltage for MasterBlaster output driver
7 NC No connect
8 - No connection
9 TDI Data to device
10 GND Signal ground
Table 27. Multi-ICE Connector Signals (Part 1 of 2)
Pin Signal Description Direction
1 VCC Power supply N/A
2 VCC Power supply N/A
3 PROC_NTRTST Processor reset Output
4 GND Ground N/A
5 PROC_TDI Processor test data input Input
6 GND Ground N/A
7 PROC_TMS Processor test mode select Input
8 GND Ground N/A
9 PROC_TCK Processor test clock input Input
10 GND Ground N/A
11 GND Ground N/A
12 GND Ground N/A
13 PROC_TDO Processor test data output O
14 GND Ground N/A